Hitachi H8/3637 Hardware Manual page 250

(2) Clock: The clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in
serial control register 3 (SCR3). See table 10.12 for the settings. Either an internal clock source
can be used to run the built-in baud rate generator, or an external clock source can be input at pin
SCK .
3
When an external clock source is input to pin SCK
desired bit rate.
When an internal clock source is used, SCK
has the same frequency as the serial bit rate, and is synchronized as in figure 10.6 so that the rising
edge of the clock occurs in the center of each bit of transmit/receive data.
Clock
0
Serial
data
Figure 10.6 Phase Relation of Output Clock and Communication Data in Asynchronous
(3) Data Transmit/Receive Operations
SCI3 Initialization: Before data is sent or received, bits TE and RE in serial control register 3
(SCR3) must be cleared to 0, after which initialization can be performed using the procedure.
Note: When modifying the operation mode, transfer format or other settings, always be sure to
clear bits TE and RE first. When TE is cleared to 0, bit TDRE will be set to 1. Clearing
RE does not clear the status flags RDRF, PER, FER, or OER, or alter the contents of the
receive data register (RDR).
When an external clock is used in asynchronous mode, do not stop the clock during operation,
including during initialization.
246
D0 D1 D2 D3
1 character (1 frame)
Mode (8-Bit Data, Parity Bit Added, and 2 Stop Bits)
, it should have a frequency 16 times the
3
can be used as the clock output pin. The clock output
3
D4 D5 D6 D7 0/1 1 1