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Bit 5—Transmit Enable (TE): Bit 5 enables or disables the start of a transmit operation.
Bit 5: TE
0
1
Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SSR) is fixed
at 1. Transmit operations are disabled, but the TXD pin functions as the transmit data
pin. To use the TXD pin as an I/O pin, clear bit TXD in PMR6 to 0.
2. In this state, writing transmit data in TDR clears bit TDRE in SSR to 0 and starts serial
data transmission.
Before setting TE to 1 it is necessary to set the transmit format in SMR.
Bit 4—Receive Enable (RE): Bit 4 enables or disables the start of a receive operation.
Bit 4: RE
0
1
Notes: 1. When RE is cleared to 0, this has no effect on the SSR flags RDRF, FER, PER, and
OER, which retain their states.
2. Serial data receiving begins when, in this state, a start bit is detected in asynchronous
mode, or serial clock input is detected in synchronous mode.
Before setting RE to 1 it is necessary to set the receive format in SMR.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Bit 3 enables or disables multiprocessor
interrupt requests. This setting is valid only in asynchronous mode, and only when the
multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1. It applies only to data
receiving. This bit is ignored when COM is set to 1 or when bit MP is cleared to 0.
Bit 3: MPIE
0
1
Note: * SCI3 does not transfer receive data from RSR to RDR, does not detect receive errors, and
does not set status flags RDRF, FER, and OER in SSR. Until a multiprocessor bit value of 1
is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are
disabled and serial status register (SSR) flags RDRF, FER, and OER are not set. When the
multiprocessor bit receives a 1, the MPBR bit of SSR is set to 1, MPIE is automatically
cleared to 0, RXI and ERI interrupts are enabled (provided bits TIE and RIE in SCR3 are
set to 1), and setting of the RDRF, FER, and OER flags is enabled.
228
Description
Transmit operation disabled *
Transmit operation enabled *
Description
Receive operation disabled *
Receive operation enabled *
Description
Multiprocessor interrupt request disabled (ordinary receive operation)
[Clearing condition]
Multiprocessor bit receives a data value of 1
Multiprocessor interrupt request enabled*
1
(TXD is the transmit data pin)
2
(TXD is the transmit data pin)
1
(RXD is a general I/O port)
2
(RXD is the receive data pin)
(initial value)
(initial value)
(initial value)
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