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Bit 7—Clock Select (CKS): Bits CKS and CKS1 select the A/D conversion speed.
Bit 5: CKS1
Bit 7: CKS
0
0
1
1
0
1
Note: * Operation is not guaranteed if the conversion time is less than 12.4 µs. Set the bits to get a
value of at least 12.4 µs.
Bit 6—External Trigger Select (TRGE): Bit 6 enables or disables the start of A/D conversion by
external trigger input.
Bit 6: TRGE
0
1
Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of the interrupt edge select
register (IEGR). See 3.3.2 for details.
Bit 5—Clock Select 1 (CKS1): Bits CKS and CKS1 select the A/D conversion speed. See bit 7,
clock select (CKS) for details.
Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0—Channel Select 3 to 0 (CH3 to CH0): Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3:
Bit 2:
CH3
CH2
0
0
1
1
0
1
Note: * Don't care
Conversion Period
Reserved (initial value)
124/ø
62/ø
31/ø
Description
Disables start of A/D conversion by external trigger
Enables start of A/D conversion by rising or falling edge of external trigger at
pin ADTRG*
Bit 1:
Bit 0:
CH1
CH0
*
*
*
*
0
0
1
1
0
1
*
*
ø = 2 MHz
—
62 µs
31 µs
15.5 µs
Analog Input Channel
No channel selected
Reserved
AN
4
AN
5
AN
6
AN
7
Reserved
Conversion Time
ø = 5 MHz
—
24.8 µs
12.4 µs
—*
(initial value)
(initial value)
285
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