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5. After data transmission is complete, bit IRRS1 in interrupt request register 1 (IRR1) is
set to 1.
When an internal clock is used, a serial clock is output from pin SCK
transmit data. After data transmission is complete, the serial clock is not output until the next time
the start flag is set to 1. During this time, pin SO
transmitted.
When an external clock is used, data is transmitted in synchronization with the serial clock input at
pin SCK
. After data transmission is complete, an overrun occurs if the serial clock continues to be
1
input; no data is transmitted and the SCSR1 overrun error flag (bit ORER) is set to 1.
While transmission is stopped, the output value of pin SO
SCSR1.
Receiving: A receive operation is carried out as follows.
1. Set bits SI1 and SCK1 in PMR2 to 1, selecting the SI
2. Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous
transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes
the internal state of SCI1.
3. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and receives data at pin SI
4. After data reception is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1.
5. Read the received data from SDRL and SDRU, as follows.
8-bit transfer mode:
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
6. After data reception is complete, an overrun occurs if the serial clock continues to be input; no
data is received and the SCSR1 overrun error flag (bit ORER) is set to 1.
Simultaneous Transmit/Receive: A simultaneous transmit/receive operation is carried out as
follows.
1. Set bits SO1, SI1, and SCK1 in PMR2 to 1, selecting the SO
necessary, set bit POF1 in PMR2 for NMOS open drain output at pin SO
2. Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous
transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes
the internal state of SCI1.
3. Write transmit data in SDRL and SDRU, as follows.
8-bit transfer mode:
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
4. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO
Receive data is input at pin SI
5. After data transmission and reception are complete, bit IRRS1 in IRR1 is set to 1.
218
SDRL
SDRL
.
1
continues to output the value of the last bit
1
can be changed by rewriting bit SOL in
1
and SCK
pin functions.
1
1
, SI
1
1
in synchronization with the
1
.
1
, and SCK
pin functions. If
1
.
1
.
1
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