Direct Transfer Time - Hitachi H8/3637 Hardware Manual

to 1, and bit TMA3 in TMA is set to 1, a transition is made directly to active (medium-speed)
mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed.
5.8.2

Direct Transfer Time

Time for Direct Transfer from Active (High-Speed) Mode to Active (Medium-Speed)
Mode: When a SLEEP instruction is executed in active (high-speed) mode while the SSBY
bit in SYSCR1 is cleared to 0, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in
SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made directly to
active (medium-speed) mode. In this case, the time from execution of the SLEEP instruction
to the end of interrupt exception handling (the direct transfer time) is given by equation (1)
below:
Direct transfer time ={ (Number of SLEEP instruction execution states) +
Example: H8/3637 Series direct transfer time = (2 + 1) × 2t
Legend: t : OSC clock cycle time
osc
t : System clock (ø) cycle time
cyc
Time for Direct Transfer from Active (Medium-Speed) Mode to Active (High-Speed)
Mode: When a SLEEP instruction is executed in active (medium-speed) mode while the
SSBY bit in SYSCR1 is cleared to 0, the LSON bit in SYSCR1 is cleared to 0, the MSON bit
in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made
directly to active (high-speed) mode. In this case, the time from execution of the SLEEP
instruction to the end of interrupt exception handling (the direct transfer time) is given by
equation (2) below:
Direct transfer time ={ (Number of SLEEP instruction execution states) +
Example: H8/3637 Series direct transfer time = (2 + 1) × 16t
Legend: t : OSC clock cycle time
osc
t : System clock (ø) cycle time
cyc
102
(number of internal processing states) } × (t
(number of interrupt exception handling execution states) ×
(t after transition) ...................................................................... (1)
cyc
(number of internal processing states) } × (t
(number of interrupt exception handling execution states) ×
(t after transition) ...................................................................... (2)
cyc
before transition) +
cyc
+ 14 × 16t
= 230t
osc osc
before transition) +
cyc
+ 14 × 2t
= 76t
osc osc osc
osc