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IRR2—Interrupt request register 2
Bit
IRRDT
Initial value
Read/Write
R/W
A/D converter interrupt request flag
0 [Clearing condition]
1 [Setting condition]
Direct transfer interrupt request flag
0 [Clearing condition]
When IRRDT = 1, it is cleared by writing 0
1 [Setting condition]
A SLEEP instruction is executed when DTON = 1 and a direct transfer is made
*
Note:
Only a write of 0 for flag clearing is possible.
7
6
IRRAD
0
0
R/W
*
*
Timer G interrupt request flag
0 [Clearing condition]
When IRRTG = 1, it is cleared by writing 0
1 [Setting condition]
When pin TMIG is set to TMIG input and the designated signal edge is detected
When IRRAD = 1, it is cleared by writing 0
When A/D conversion is completed and ADSF is reset
5
4
3
—
IRRTG
IRRTFH
0
0
0
—
R/W
R/W
*
Timer FL interrupt request flag
0 [Clearing condition]
1 [Setting condition]
Timer FH interrupt request flag
0 [Clearing condition]
When IRRTFH = 1, it is cleared by writing 0
1 [Setting condition]
When counter FH matches output compare register
FH in 8-bit mode, or when 16-bit counter F (TCFL,
TCFH) matches 16-bit output compare register F
(OCRFL, OCRFH) in 16-bit mode
H'F7
System control
2
1
IRRTFL
IRRTY
0
0
R/W
R
*
*
Timer Y interrupt request clear flag
This is a special bit for clearing the
IRRTY interrupt request flag. Writing
0 to this bit clears bit 1 (IRRTY) to 0.
Note that writing 0 to this bit does not
give the bit itself a value of 0.
This bit is always read as 1, and only
a write of 0 to this bit is valid.
Timer Y interrupt request flag
0 [Clearing condition]
When IRRTY is 1, it is cleared
by writing 0 to IRRTYC
1 [Setting condition]
When the timer Y counter value
overflows (from H'FFFF to H'0000)
Note: This bit is read-only. It is cleared
by writing 0 to bit 0 (IRRTYC).
When IRRTFL = 1, it is cleared by writing 0
When TCFL matches in 8-bit mode
0
IRRTYC
1
W*
373
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