Table of Contents
Advertisement
3. From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to
table 3.2 for a list of interrupt priorities.)
4. The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is
accepted; if the I bit is 1, the interrupt request is held pending.
5. If the interrupt is accepted, after processing of the current instruction is completed, both PC
and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4.
The PC value pushed onto the stack is the address of the first instruction to be executed upon
return from interrupt handling.
6. The I bit of CCR is set to 1, masking all further interrupts.
7. The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
clearing bits in an interrupt request register, always do so while interrupts are masked
(I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.
71
Advertisement
Table of Contents
