Table A.3
Number of Cycles in Each Instruction
Execution Status
(Instruction Cycle)
Instruction fetch
Branch address read
Stack operation
Byte data access
Word data access
Internal operation
Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for
details.
326
On-Chip Memory
S
2
I
S
J
S
K
S
L
S
M
S
1
N
Access Location
On-Chip Peripheral Module
—
2 or 3*
—
1