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5.3
Standby Mode
5.3.1
Transition to Standby Mode
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in timer mode
register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and
on-chip peripheral modules stop functioning. As long as a minimum required voltage is applied,
the contents of the CPU registers and some on-chip peripheral function internal registers, and data
in the on-chip RAM, will be retained. The I/O ports go to the high-impedance state.
5.3.2
Clearing Standby Mode
Standby mode is cleared by an interrupt (IRQ
Clearing by Interrupt: When an interrupt is requested, the system clock pulse generator starts.
After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is
supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts.
Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-
speed) mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the
particular interrupt is disabled in the interrupt enable register.
Clearing by RES Input: When the RES pin goes low, the system clock pulse generator starts.
After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset
exception handling.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin should be kept at the low level until the pulse generator
output stabilizes.
94
, IRQ
, WKP
to WKP
0
1
0
) or by input at the RES pin.
7
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