Texas Instruments TMS320C6455 User Manual
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Texas Instruments TMS320C6455 User Manual

Dsp ddr2 memory controller
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TMS320C6455/C6454 DSP
DDR2 Memory Controller
User's Guide
Literature Number: SPRU970G
December 2005 – Revised June 2011

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  • Page 1 TMS320C6455/C6454 DSP DDR2 Memory Controller User's Guide Literature Number: SPRU970G December 2005 – Revised June 2011...
  • Page 2 SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated...

  • Page 3: Table Of Contents

    SDRAM Timing 1 Register (SDTIM1) SDRAM Timing 2 Register (SDTIM2) Burst Priority Register (BPRIO) DDR2 Memory Controller Control Register (DMCCTL) Revision History SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Contents Table of Contents...
  • Page 4 SDRAM Timing 1 Register (SDTIM1) SDRAM Timing 2 Register (SDTIM2) Burst Priority Register (BPRIO) DDR2 Memory Controller Control Register (DMCCTL) List of Figures List of Figures Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback...
  • Page 5 SDRAM Timing 2 Register (SDTIM2) Field Descriptions Burst Priority Register (BPRIO) Field Descriptions DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback List of Tables Copyright © 2005–2011, Texas Instruments Incorporated List of Tables...
  • Page 6 SPRU970G – December 2005 – Revised June 2011 List of Tables Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated...

  • Page 7: Preface

    About This Manual This document describes the DDR2 memory controller in the TMS320C6455/C6454 digital signal processors (DSPs). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
  • Page 8 SPRU970G – December 2005 – Revised June 2011 Read This First Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated...

  • Page 9: Introduction

    SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback SPRU970G – December 2005 – Revised June 2011 C6455/C6454 DDR2 Memory Controller Copyright © 2005–2011, Texas Instruments Incorporated User's Guide Figure 1). Master C6455/C6454 DDR2 Memory Controller...

  • Page 10: Industry Standard(S) Compliance Statement

    Configuration Register file A registers Master L1 data memory controller Slave Cache control Memory protection Bandwidth management cache/SRAM Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com Advanced event triggering (AET) Instruction fetch SPLOOP buffer 16/32−bit instruction dispatch Instruction decode Data path B...

  • Page 11: Peripheral Architecture

    Two on-die termination output signals (DEODT[1:0]). (These pins are reserved for future use.) SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Figure 2 and described in Copyright © 2005–2011, Texas Instruments Incorporated Peripheral Architecture Section 3 Table 1. The following...

  • Page 12: Ddr2 Memory Controller Signals

    C6455/C6454 DDR2 Memory Controller DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDWE DSDRAS DSDCAS DDR2 DSDDQM[3:0] Memory DSDDQS[3:0] Controller DSDDQS[3:0] DBA[2:0] DEA[13:0] DED[31:0] DEODT[1:0] DSDDQGATE[3:0] REFSSTL DDRSLRATE Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback...

  • Page 13: Protocol Description(S)

    BA refers to the bank address pins (BA[2:0]). SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Table 2. DDR2 SDRAM Commands DCE0 DSDRAS DSDCAS Copyright © 2005–2011, Texas Instruments Incorporated Peripheral Architecture Table Table 3 shows the BA[2:0] A[13:11, 9:0]...

  • Page 14: Ddr2 Mrs And Emrs Command

    Figure 3. DDR2 MRS and EMRS Command DDR2CLKOUT DDR2CLKOUT DSDCKE DCE0 DSDRAS DSDCAS DSDWE DEA[13:0] DBA[2:0] C6455/C6454 DDR2 Memory Controller Section 2.11. MRS/EMRS BANK Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback...

  • Page 15: Refresh Command

    SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Section 2.8 for more details on REFR command Figure 4. Refresh Command REFR Copyright © 2005–2011, Texas Instruments Incorporated Peripheral Architecture (Figure 4). REFR is C6455/C6454 DDR2 Memory Controller...

  • Page 16: Actv Command

    Figure 5 shows an example of an ACTV command. Reads or writes to Figure 5. ACTV Command ACTV BANK Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com is incurred before a SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback...

  • Page 17: Dcab Command

    DBA[2:0] DSDDQM[3:0] SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Figure 6 shows the timing diagram for a DCAB command. Figure 6. DCAB Command DCAB Copyright © 2005–2011, Texas Instruments Incorporated Peripheral Architecture C6455/C6454 DDR2 Memory Controller...

  • Page 18: Deac Command

    DSDCKE DCE0 DSDRAS DSDCAS DSDWE DEA[13:11, 9:0] DEA[10] DBA[2:0] DSDDQM[3:0] C6455/C6454 DDR2 Memory Controller Figure 7. DEAC Command DEAC Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com Figure 7 shows SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback...

  • Page 19: Ddr2 Read Command

    SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Figure 8. Read latency is equal to CAS latency plus additive latency. Figure 8. DDR2 READ Command CAS Latency Copyright © 2005–2011, Texas Instruments Incorporated Peripheral Architecture C6455/C6454 DDR2 Memory Controller...

  • Page 20: Memory Width, Byte Alignment, And Endianness

    Maximum Addressable Bytes Address Type Generated by DDR2 Memory Controller 256M bytes Halfword address 512M bytes Word address Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com DQM7 DQM8 Table 4 summarizes the SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback...

  • Page 21: Address Mapping

    256 words (requires 8 column address bits) 512 words (requires 9 column address bits) 1024 words (requires 10 column address bits) 2048 words (requires 11 column address bits) Copyright © 2005–2011, Texas Instruments Incorporated Peripheral Architecture DED[7:0] (Byte Lane 0)

  • Page 22: Logical Address-To-Ddr2 Sdram Address Map For 32-Bit Sdram

    Logical Address 21:16 nrb=14 nrb=14 nrb=14 nrb=14 nrb=14 nrb=14 nrb=14 nrb=14 nrb=14 nrb=14 nrb=14 nrb=14 nrb=14 Figure Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com nrb=14 nrb=14 nbb=1 nbb=2 nbb=3 nrb=14 ncb=9 nbb=1 ncb=9 nbb=2 ncb=9 nbb=3 ncb=9 ncb=10 nbb=1...

  • Page 23: Logical Address-To-Ddr2 Sdram Address Map

    1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1. SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Col. 3 Col. 4 Col. M−1 Copyright © 2005–2011, Texas Instruments Incorporated Peripheral Architecture Col. M Row 0, bank 0 Row 0, bank 1 Row 0, bank 2...

  • Page 24: Ddr2 Memory Controller Interface

    Stores read data coming from memory to on-chip requestors C6455/C6454 DDR2 Memory Controller Bank 2 Row 0 Row 1 Row 2 Row N Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com Bank P 0 1 2 3 Row 0 Row 1 Row 2 Row N...

  • Page 25: Ddr2 Memory Controller Fifo Block Diagram

    Following this scheduling, each master may have one command ready for execution. SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Command/Data Scheduler Registers Copyright © 2005–2011, Texas Instruments Incorporated Peripheral Architecture Command to Memory Write Data to Memory Read Data...
  • Page 26 Burst Priority Register (BPRIO) sets the number of the transfers that must be made before the DDR2 memory controller will raise the priority of the oldest command. C6455/C6454 DDR2 Memory Controller Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com Section 2.8) being...

  • Page 27: Refresh Scheduling

    Backlog count is greater than 11. Indicates the level at which the DDR2 memory controller should perform a REFR command before servicing new memory access requests. SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Table 7. Refresh Urgency Levels Copyright © 2005–2011, Texas Instruments Incorporated Peripheral Architecture C6455/C6454 DDR2 Memory Controller...

  • Page 28: Self-Refresh Mode

    C6455/C6454 DDR2 Memory Controller Effect Resets control logic and all DDR2 memory controller registers Resets control logic and interrupt registers Section 2.11.2. Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com Initiated by: Power on reset Warm reset Max reset System reset CPU reset Section 2.11.2...

  • Page 29: Ddr2 Sdram Mode Register Configuration

    SDCFG.DDR_DRIVE Output driver impedance control bits. Initialized using the DDR_DRIVE bit of the SDRAM configuration register (SDCFG). DLL enable/disable bits. DLL is always enabled. Copyright © 2005–2011, Texas Instruments Incorporated Peripheral Architecture C6455/C6454 DDR2 Memory Controller...

  • Page 30: 2.12 Interrupt Support

    The DDR2 memory controller will remain fully functional during emulation halts to allow emulation access to external memory. C6455/C6454 DDR2 Memory Controller Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback...

  • Page 31: Using The Ddr2 Memory Controller

    For more information, see the device-specific data manual. SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback show a high-level view of the three memory topologies Copyright © 2005–2011, Texas Instruments Incorporated Using the DDR2 Memory Controller C6455/C6454 DDR2 Memory Controller...

  • Page 32: Connecting To Two 16-Bit Ddr2 Sdram Devices

    DSDDQGATE0 DSDDQGATE1 DSDDQGATE2 DSDDQGATE3 These pins are used as a timing reference during memory reads. For routing rules, see the device-specific data manual. C6455/C6454 DDR2 Memory Controller Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com DDR2 Memory x16-bit LDQS LDQS UDQS...

  • Page 33: Connecting To A Single 16-Bit Ddr2 Sdram Device

    These pins are used as a timing reference during memory reads. For routing rules, see the device-specific data manual. SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Copyright © 2005–2011, Texas Instruments Incorporated Using the DDR2 Memory Controller DDR2 Memory...

  • Page 34: Connecting To Two 8-Bit Ddr2 Sdram Devices

    DSDDQGATE0 DSDDQGATE1 DSDDQGATE2 DSDDQGATE3 These pins are used as a timing reference during memory reads. For routing rules, see the device-specific data manual. C6455/C6454 DDR2 Memory Controller Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com DDR2 Memory x8-bit RDQS RDQS BA[2:0]...

  • Page 35: Configuring Ddr2 Memory Controller Registers To Meet Ddr2 Sdram Specifications

    To configure the DDR2 memory controller for a 32-bit data bus width. To select a CAS latency of 4. To select 8 internal DDR2 banks. To select 1024-word page size. Copyright © 2005–2011, Texas Instruments Incorporated Using the DDR2 Memory Controller Figure 16, where each device has the...

  • Page 36: Ddr2 Memory Refresh Specification

    Activate to Activate command in the same bank Activate to Activate command in a different bank Write to read command delay Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com Value 7.8 μs Table 14 Section 4.6 for more information. Formula (Register Field Must Field Be ≥)

  • Page 37: Sdtim2 Configuration

    3 (t Table 16. DMCCTL Configuration Description Programmed to be out of reset. Read latency is equal to CAS latency + 1. Copyright © 2005–2011, Texas Instruments Incorporated Using the DDR2 Memory Controller Formula (Register Field Value Field Must Be ≥)

  • Page 38: Ddr2 Memory Controller Registers

    DDR2 Memory Controller Status Register SDRAM Configuration Register SDRAM Refresh Control Register SDRAM Timing 1 Register SDRAM Timing 2 Register Burst Priority Register DDR2 Memory Controller Control Register Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com Section Section 4.1 Section 4.2 Section 4.3 Section 4.4 Section 4.5...

  • Page 39: Module Id And Revision Register (Midr)

    Major revision. MN_REV Minor revision. SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Figure 19 MOD_ID R-0x0031 Copyright © 2005–2011, Texas Instruments Incorporated DDR2 Memory Controller Registers and described in Table MN_REV R-0x0F C6455/C6454 DDR2 Memory Controller...

  • Page 40: Ddr2 Memory Controller Status Register (Dmcstat)

    Interface logic is not ready; either powered down, not ready, or not locked. Interface logic is powered up, locked, and ready for operation. Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com Figure 20 IFRDY...

  • Page 41: Sdram Configuration Register (Sdcfg)

    SDRAM initialization sequence. 32-bit bus width. 16-bit bus width Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. Copyright © 2005–2011, Texas Instruments Incorporated DDR2 Memory Controller Registers Table DDR_DRIVE Reserved...
  • Page 42 256-word page requiring 8 column address bits. 512-word page requiring 9 column address bits. 1024-word page requiring 10 column address bits. 2048-word page requiring 11 column address bits. Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback...

  • Page 43: Sdram Refresh Control Register (Sdrfc)

    Writing a value less than 0x0100 to this field will cause it to be loaded with 2 * T_RFC value from the SDRAM Timing 1 Register. SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback and described in Table Reserved R-0x0 REFRESH_RATE R/W-0x753 Copyright © 2005–2011, Texas Instruments Incorporated DDR2 Memory Controller Registers C6455/C6454 DDR2 Memory Controller...

  • Page 44: Sdram Timing 1 Register (Sdtim1)

    AC timing parameter in the DDR2 memory section of the device-specific data manual. /DDR2CLKOUT) - 1 /DDR2CLKOUT) - 1 /DDR2CLKOUT) - 1 /DDR2CLKOUT) - 1 /DDR2CLKOUT) - 1 /DDR2CLKOUT) - 1 Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com T_RCD T_WR R/W-0x7 R/W-0x7 T_RRD...
  • Page 45 SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback /DDR2CLKOUT) - 1 + 2*t ) / (4*t )) - 1 /DDR2CLKOUT) - 1 Copyright © 2005–2011, Texas Instruments Incorporated DDR2 Memory Controller Registers AC timing parameter in the C6455/C6454 DDR2 Memory Controller...

  • Page 46: Sdram Timing 2 Register (Sdtim2)

    DSDCKE pin, minus 1. The value for these bits can be derived from the t parameter in the DDR2 section of the device-specific data manual. Calculate using this formula: T_CKE = t Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com Figure 24 and described in...

  • Page 47: Burst Priority Register (Bprio)

    EMIF reorders commands based on its arbitration. SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Section 2.7.2. Figure 25. Burst Priority Register (BPRIO) Reserved Copyright © 2005–2011, Texas Instruments Incorporated DDR2 Memory Controller Registers Figure 25 and described in Table PRIO_RAISE R/W-0xFF...

  • Page 48: Ddr2 Memory Controller Control Register (Dmcctl)

    Read latency bits. These bits must be set equal to the CAS latency + 1. C6455/C6454 DDR2 Memory Controller Figure 26 and described in Table Reserved R-0x5000 Copyright © 2005–2011, Texas Instruments Incorporated www.ti.com Rsvd Rsvd RESET R/W- R/W- R-0x0 R/W-0x7 SPRU970G –...

  • Page 49: Revision History

    Modified ODT pins in figure NOTE: Page numbers for previous revisions may differ from page numbers in the current version. SPRU970G – December 2005 – Revised June 2011 Submit Documentation Feedback Revision History Copyright © 2005–2011, Texas Instruments Incorporated Revision History Revision History...

  • Page 50: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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