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Texas Instruments TPS65987D Manual

Texas Instruments TPS65987D Manual

Usb type-c and usb pd controller with integrated source and sink power path supporting usb3 and alternate mode

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TPS65987D USB Type-C
Power Path Supporting USB3 and Alternate Mode
1 Features
This device is certified by the USB-IF for PD3.0
– PD3.0 silicon is required for certification of new
USB PD designs
TID#: 1067
– Article on
PD2.0 vs. PD3.0
TPS65987D is a fully configurable USB PD device
controller:
– Ability to source and sink up to 20 V/5 A
– Alternate mode support
DisplayPort
– Control for external DC/DC supplies, high
speed data muxes, and other peripheral
devices through either GPIO or I2C
Ex:
TPS65987EVM
Ex:
TIDA-050012
– GUI tool to easily configure TPS65987D for
various applications:
– Power management
Power supply from 3.3 V or VBUS source
3.3-V LDO output for dead battery support
– For a more extensive selection guide and
getting started information, please refer to
www.ti.com/usb-c
and
Integrated fully managed power paths:
– Two integrated 20-V, 5-A, 25-mΩ source or sink
load switch
– UL 2367 cert #: 20190107-E169910
– IEC 62368-1 cert #: US-34617-UL
Integrated robust power path protection
– Integrated reverse current protection,
undervoltage protection, overvoltage protection,
and slew rate control for both 20-V/5-A power
paths when configured to Sink
– Integrated undervoltage protection, overvoltage
protection, and current limiting for inrush
current protection for both 20-V/5-A power
paths when configured to Source
USB Type-C
®
Power Delivery (PD) controller
– 13 configurable GPIOs
– BC1.2 charging support
– USB PD 3.0 certified
– USB Type-C specification certified
– Cable attach and orientation detection
– Integrated VCONN switch
– Physical layer and policy engine
– 3.3-V LDO output for dead battery support
– Power supply from 3.3 V or VBUS source
– 1 I2C primary or secondary port
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
®
and USB PD Controller with Integrated Source and Sink
TPS65988X-CONFIG
E2E guide
SLVSES1D – MAY 2018 – REVISED OCTOBER 2022
– 1 I2C primary only port
– 1 I2C secondary only port
2 Applications
Single board computer
Power
tools,
power
banks,
payment
Wireless
speakers,
headphones
Other
personal electronics
applications
Docking station
Flat panel monitor
3 Description
The TPS65987D is a stand-alone USB Type-C and
Power Delivery (PD) controller providing cable plug
and orientation detection for a single USB Type-C
connector. Upon cable detection, the TPS65987D
communicates on the CC wire using the USB
PD protocol. When cable detection and USB PD
negotiation are complete, the TPS65987D enables
the appropriate power path and configures alternate
mode settings for external multiplexers.
Device Information
PART NUMBER
PACKAGE
TPS65987D
QFN (RSH56)
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
5-20 V
5 A
5-20 V
5 A
3.3 V
Type-C Cable Detection
Host
Host
USB PD Controller
Interface
TPS65987D
Alternate Mode Mux Ctrl
GPIO or I2C
SuperSpeed Mux/Retimer
Simplified Schematic
TPS65987D
retail automation and
and
industrial
(1)
BODY SIZE (NOM)
7.00 mm x 7.00 mm
V
BUS
CC1/2
CC
2
V
and
CONN
USB
Type-C
Connector
D+/-
2
BC1.2
USB P/N
GND

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Summary of Contents for Texas Instruments TPS65987D

  • Page 1 TID#: 1067 payment – Article on PD2.0 vs. PD3.0 • Wireless speakers, headphones • TPS65987D is a fully configurable USB PD device • Other personal electronics industrial controller: applications – Ability to source and sink up to 20 V/5 A •...
  • Page 2 Correct Pin Numbers ............Changes from Revision * (May 2018) to Revision A (August 2018) Page • Changed status from Advance Information to Production Data................1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 3 PP_HV1 -11 32- I2C2_SCL DRAIN1 PP_HV1 -12 31- HPD2 (GPIO4) 30- HPD1 (GPIO3) VBUS1 -13 29- I2C1_IRQ VBUS1 -14 Figure 5-1. RSH Package 56-Pin QFN Top View Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65987D...
  • Page 4 General Purpose Digital I/O 0. Float pin when unused. GPIO0 is asserted low during GPIO0 Input (High-Z) the TPS65987D boot process. Once device configuration and patches are loaded GPIO0 is released General Purpose Digital I/O 1. Ground pin with a...
  • Page 5 Input SPI chip select. Ground pin when unused Port side of first VBUS power switch. Bypass with VBUS1 13, 14 — capacitor to ground. Tie to VBUS2 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65987D...
  • Page 6 Reset State indicates the state of a given pin immediately following power application, prior to any configuration from firmware. I = input, O = output, I/O = bidirectional, GND = ground, PWR = power, NC = no connect Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 7 Operating junction temperature, T –10 All voltage values are with respect to underside power pad. Underside power pad must be directly connected to ground plane of the board. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65987D...
  • Page 8 Forward voltage drop across VIN_3V3 = 50 mA FWD_DROP LOAD to LDO_3V3 switch Recommended capacitance on μF LDO_3V3 LDO_3V3 pin Recommended capacitance on μF LDO_1V8 LDO_1V8 pin SUPERVISORY Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 9 PP_CABLE to PPCC = 85C C_CCn Active quiescent current from PP_HV Source Configuration, Comparator HVACT pin, EN_HV = 1 RCP function enabled, I = 100mA LOAD Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65987D...
  • Page 10 V/ms LOAD Diode Mode Reverse current blocking voltage REVPHV threshold for PP_HV switch Comparator Mode Voltage that is a safe 0 V per USB- SAFE0V PD specification Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 11 0.15 0.25 H_CCA_USB advertising Default USB current capability. Voltage Threshold for detecting active cables attach when configured as a Source and 0.35 0.45 H_CCA_1P5 advertising 1.5A capability. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65987D...
  • Page 12 Port configured as Sink RXTF Rx receive falling input threshold Port configured as Source RXTF Number of transitions for signal NCOUNT detection (number to count to detect non-idle bus). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 13 5µA pulled from Cx_USB_N pin kΩ _102k VCx_USB_P Cx_USB_P Output Voltage No load on Cx_USB_P 1.12 1.28 _1.2V VCx_USB_N Cx_USB_N Output Voltage No load on Cx_USB_N 1.12 1.28 _1.2V Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65987D...
  • Page 14 IO = 2 mA, LDO_3V3 = 3.3 V I2C_IRQx OD_VOL Low-level output voltage = 2 mA OD_LKG Leakage current Output is Hi-Z, VIN = 0 to LDO_3V3 –1 µA Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 15 SDA AND SCL FAST MODE CHARACTERISTICS ƒ C clock frequency Configured as Slave ƒ C clock frequency Configured as Master SCL_MASTER C clock high time µs HIGH Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65987D...
  • Page 16 DP SINK SIDE (HPD HPD_HDB_SEL = 0 µs HPD high debounce time HPD_HDB HPD_HDB_SEL = 1 HPD low debounce time µs HPD_LDB HPD IRQ limit time 1.35 1.65 HPD_IRQ Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 17 TPS65987D www.ti.com SLVSES1D – MAY 2018 – REVISED OCTOBER 2022 6.18 Typical Characteristics Temperature (°C) D004 Figure 6-1. PPHVx Rdson vs Junction Temperature Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65987D...
  • Page 18 SPI_CSZ t dact t dinact SPI_CLK t dpico t dpico SPI_PICO Valid Data t supoci SPI_POCI Valid Data t hdpoci Figure 7-2. SPI Controller Timing Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 19 The TPS65987D is a fully-integrated USB Power Delivery (USB-PD) management device providing cable plug and orientation detection for a USB Type-C and PD plug or receptacles. The TPS65987D communicates with the cable and another USB Type-C and PD device at the opposite end of the cable, enables integrated port power switch, controls an external high current port power switch, and negotiates alternate modes .
  • Page 20 8.3 Feature Description 8.3.1 USB-PD Physical Layer Figure 8-1 shows the USB PD physical layer block surrounded by a simplified version of the analog plug and orientation detection block. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 21 USB-PD transmitter. Figure 8-3 illustrates the high-level block diagram of the baseband USB-PD receiver. 4b5b Data to PD_TX Encoder Encoder Figure 8-2. USB-PD Baseband Transmitter Block Diagram Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65987D...
  • Page 22 8.3.1.4 USB-PD BMC Transmitter The TPS65987D transmits and receives USB-PD data over one of the C_CCn pins for a given CC pin pair (one pair per USB Type-C port). The C_CCn pins are also used to determine the cable orientation (see the Section 8.3.4...
  • Page 23 Figure 8-7. ZDRIVER Circuit 8.3.1.5 USB-PD BMC Receiver The receiver block of the TPS65987D receives a signal that falls within the allowed Rx masks defined in the USB PD specification. The receive thresholds and hysteresis come from this mask. Copyright © 2022 Texas Instruments Incorporated...
  • Page 24 8.3.2.2 VBUS LDO The TPS65987D contains an internal high-voltage LDO which is capable of converting up to 22 V from VBUS to 3.3 V for powering internal device circuitry. The VBUS LDO is only utilized during dead battery operation while the VIN_3V3 supply is not present.
  • Page 25 The other way a supply switch-over occurs is when both supplies are present and VIN_3V3 is removed and falls below 2.85 V. In this case, a hard reset of the TPS65987D is initiated by device firmware, prompting a re-boot.
  • Page 26 8.3.3.1.2 PP_HV Over Current Protection The TPS65987D continuously monitors the forward voltage drop across the internal power switches. When a forward drop corresponding to a forward current of I is detected the internal power switch is latched off to protect the internal switches as well as upstream power supplies.
  • Page 27 8.3.3.4 PP_CABLE Power Switch The TPS65987D has an integrated 5-V unidirectional power mux that is rated for up to 600 mA of current. The mux may supply power to either of the port CC pins for use as VCONN power.
  • Page 28 8.3.3.4.2 PP_CABLE Input Good Monitor The TPS65987D monitors the voltage at the PP_CABLE pins prior to enabling the power switch. If the voltage at PP_CABLE exceeds the input good threshold the switch is allowed to close, otherwise the switch remains open.
  • Page 29 8.3.4.1 Configured as a DFP When one of the TPS65987D ports is configured as a DFP, the device detects when a cable or a UFP is attached using the C_CC1 and C_CC2 pins. When in a disconnected state, the TPS65987D monitors the voltages on these pins to determine what, if anything, is connected.
  • Page 30 Figure 8-15. Fast Role Swap Detection and Signaling When a TPS65987D port is operating as a sink with FRS enabled, the TPS65987D monitors the CC pin voltage. If the CC voltage falls below VTH_FRS a fast role swap situation is detected and signaled to the digital core.
  • Page 31 8.3.5.2 BUSPOWER (ADCIN1) The BUSPOWERz input to the internal ADC controls the behavior of the TPS65987D in response to VBUS being supplied during a dead battery condition. The pin must be externally tied to the LDO_3V3 output via a resistive divider.
  • Page 32 BC1.2 compliant charger, as well as advertise BC1.2 charging capabilities to connected devices. To enable the required detection and advertisement mechanisms, the block integrates various voltage sources, currents, and resistances. Figure 8-18 shows the connection of these elements to the TPS65987D C_USB_P and C_USB_N pins. VLGC_HI IDP_SRC...
  • Page 33 The Charging Downstream Port (CDP) advertisement follows the USB BC1.2 specification. The advertisement scheme monitors the D+ line using the ADC. When a voltage of 0.6V is seen on the D+ line, TPS65987D forces a voltage of 0.6 V on the D– line until the D+ goes low. The voltage source VDX_SRC and the current source IDX_SNK, are activated during CDP advertisement.
  • Page 34 PD messaging. When one of the TPS65987D's ports is operating as a DP source, its corresponding HPD pin operates as an output (HPD TX), and when a port is operating as a DP sink, its corresponding HPD pin operates as an input (HPD RX).
  • Page 35 I2C_SDA/SCL I2C_DO Figure 8-20. I C Buffer 8.3.9.3 SPI The TPS65987D has a single SPI controller interface for use with external memory devices. Figure 8-21 shows the I/O buffers for the SPI interface. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback...
  • Page 36 Figure 8-21. SPI buffer 8.3.10 PWM Driver The TPS65987D includes two integrated PWM drivers which may be multiplexed onto GPIO 14 and GPIO 15. The PWM driver implements an 8-bit counter driven by either the internal 100-kHz clock or internal 24-MHz clock.
  • Page 37 C Port 2 is comprised of the I2C2_SDA, I2C2_SCL, and I2C2_IRQ pins. These interfaces provide general status information about the TPS65987D, as well as the ability to control the TPS65987D behavior, as well as providing information about connections detected at the USB-C receptacle and supporting communications to/from a connected device and/or cable supporting BMC USB-PD.
  • Page 38 SLVSES1D – MAY 2018 – REVISED OCTOBER 2022 8.3.12.1 I C Interface Description The TPS65987D support Standard and Fast mode I C interface. The bidirectional I C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up resistor.
  • Page 39 Note 1: Any bit is maskable for each port independently, providing firmware override of the I C address. Note The TPS65987D I2C address values are set and controlled by device firmware. Certain firmware configurations may override the presented address settings. 8.3.12.4 Unique Address Interface The Unique Address Interface allows for complex interaction between an I C master and a single TPS65987D.
  • Page 40 C Pin Address Setting (ADCIN2) To enable the setting of multiple I C addresses using a single TPS65987D pin, a resistor divider is placed externally on the ADCIN2 pin. The internal ADC then decodes the address from this divider value.
  • Page 41 IC must support 12 MHz SPI clock frequency. The size of the flash must be at least 64 kB. The SPI controller of the TPS65987D supports SPI Mode 0. For Mode 0, data delay is defined such that data is output on the same cycle as chip select (SPI_CS pin) becomes active.
  • Page 42 8.3.15 Oscillators The TPS65987D has two independent oscillators for generating internal clock domains. A 24-MHz oscillator generates clocks for the core during normal operation. A 100-kHz oscillator generates clocks for various timers and clocking the core during low power states.
  • Page 43 5 V at 3.0 A Source capability TBT Alternate Modes not supported DisplayPort Alternate Modes not supported 8.4.2 Power States The TPS65987D may operate in one of three different power states: Active, Idle, or Sleep. The functionality available in each state is summarized in Table 8-8.
  • Page 44 Wake on PD Communication Wake on I2C Communication LDO_3V3 may be generated from either VIN_3V3 or VBUS. If LDO_3V3 is generated from VBUS, TPS65987D port only operate as sinks. Wake up from Idle to Active upon a PD message is supported however the first PD message received is lost.
  • Page 45 Initial device configuration is configured through a configuration bundle loaded onto the device during boot. The bundle may be loaded via I C or SPI. The TPS65987D configuration bundle and host interface allow the to be customized for each specific application. The configuration bundle can be generated through the...
  • Page 46 The Schottky diode will start to conduct once VBUS goes below the forward voltage. When the TPS65987D is the only device connected to VBUS place the Schottky Diode close to the VBUS pin of the TPS65987D. The two figures below show a short condition with and without a Schottky diode on VBUS. In...
  • Page 47 The TPS65987D works very well in single port Notebooks that support PD charging. The two internal power paths for the TPS65987D source System 5 V on VBUS through the PPHV2 path and sink VBUS up to 20 V on PPHV1. The TPS65987D integrated reverse current protection allows the designer to connect PPHV1 to another power source such as a standard barrel jack or proprietary dock connector power to charge the notebook battery.
  • Page 48 9.2.2.1 USB and DisplayPort Notebook Supporting PD Charging For systems that support USB and DisplayPort Data, the USB and DisplayPort sources are muxed to the Type-C connector through the TUSB1046 Super Speed mux. The TPS65987D is capable of controlling the Super Speed Mux over I C and will configure it according to the connection at the Type-C connector.
  • Page 49 A Thunderbolt system is capable of source USB, DisplayPort, and Thunderbolt data. There is an I C connection between the TPS65987D and the Thunderbolt controller. The TPS65987D will determine the connection on the Type-C and will generate an interrupt to the Thunderbolt controller to generate the appropriate data output. An external mux for SBU may be needed to mux the LSTX/RX and AUX_P/N signal from the Thunderbolt controller to the Type-C Connector.
  • Page 50 Thunderbolt I2C2 Controller I2C Master I2C1 I2C MASTER Copyright © 2017, Texas Instruments Incorporated Figure 9-7. Thunderbolt Notebook Supporting PD Charging 9.2.2.2.1 Design Requirements Table 9-7 summarizes the Power Design parameters for an USB Type-C PD Thunderbolt Notebook. Table 9-7. Power Design Parameters...
  • Page 51 Figure 9-8. RESETN Circuit The TPS65987D and the Thunderbolt controller share the same flash and they must be able to access it at different times. The TPS65987D will access the flash first to load its configuration and then the Thunderbolt controller will read the flash for its firmware.
  • Page 52 AUX_N OUTA1- AUX_P 9.2.2.2.2.7 Thunderbolt Flash Options In most Thunderbolt systems the TPS65987D will share the flash with the Thunderbolt controller. The flash contains the Thunderbolt Controller firmware and the configuration data for the TPS65987D. Table 9-13 shows the supported SPI flash options for Thunderbolt systems.
  • Page 53 LM3489 PPHV2 5V/9V/15V/20V I2C2 I2C MASTER Copyright © 2017, Texas Instruments Incorporated Figure 9-9. USB and DisplayPort Dock Block Diagram 9.2.2.3.1 Design Requirements Table 9-14 summarizes the Power Design parameters for a USB Type-C PD docking system. Table 9-14. Power Design Parameters...
  • Page 54 Table 9-18 summarizes the TPS65987D GPIO Events and the control pins for the TUSB1064. Note that the pin strapping on the TUSB1064 will set the GPIO control mode and the required equalizer settings. For more details refer to the TUSB1064 datasheet.
  • Page 55 VBUS when VIN_3V3 is unavailable. This LDO steps down any recommended voltage on the VBUS pin. When VBUS is 20 V, as is allowable by USB PD, the internal circuitry of the TPS65987D device operates without triggering thermal shutdown; however, a significant external load on the LDO_3V3 pin can increase the temperature enough to trigger a thermal shutdown.
  • Page 56 11.1.1 Top TPS65987D Placement and Bottom Component Placement and Layout When the TPS65987D is placed on top and its components on bottom the solution size will be at its smallest. 11.2 Layout Example Follow the differential impedances for Super and High Speed signals defined by their specifications (DisplayPort - AUXN/P and USB2.0).
  • Page 57 VBUS and PPHV capacitors it is easiest to place them with the GND terminal of the capacitors to face outward from the TPS65987D or to the side since the drain connection pads on the bottom layer should not be connected to anything and left floating.
  • Page 58 On the top side, create pours for PP_HV1/2 and VBUS1/2 to extend area to place 8-mil hole and 16-mil diameter vias to connect to the bottom layer. See Figure 11-7 for the recommended via sizing. Figure 11-7. Recommended Minimum Via Sizing Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 59 Most of the GPIO signals can be fanned out on the top layer with a 4-mil trace. The PP_EXT1/2 GPIO control go through a via to be routed on another layer. Figure 11-10 below shows the CC and GPIO routing. Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: TPS65987D...
  • Page 60 PCB for the thermal pads of each FET. When looking at the footprint for the TPS65987D, pins 57 and 58 are two smaller pads underneath the device.
  • Page 61 Each 8-/16-mil to 10-/20-mil via could have a thermal resistance ranging from 175°C/W to 200°C/W with board manufacturing variation. When doing thermal calculations it is recommended to use the worst case 200°C/W Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback...
  • Page 62 In this layout example, the D+/D- lines are routed to an internal layer from the connector. They are then via’d up to the TPS65987D directly at the pins. There is a small trace that is connecting the via to the pin on the top layer.
  • Page 63 Figure 11-15. Via Connection for USB2 Figure 11-16 shows the entire routing from the Type-C connector, ESD Protection, and TPS65987D BC1.2 Detection. This example does not take length matching into consideration but It is recommended to follow standard USB2 rules for routing and length matching.
  • Page 64 TPS65987D www.ti.com SLVSES1D – MAY 2018 – REVISED OCTOBER 2022 Figure 11-16. Complete USB2 Routing Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 65 All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 66 This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPS65987D...
  • Page 67 RoHS & Green Call TI Level-3-260C-168 HR -10 to 75 TPS65987D Samples The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
  • Page 69 PACKAGE OUTLINE RSH0056E VQFN - 1 mm max height SCALE 2.000 PLASTIC QUAD FLATPACK - NO LEAD 7.15 6.85 PIN 1 INDEX AREA 7.15 6.85 1 MAX SEATING PLANE 0.08 C 0.05 0.00 3.4 0.1 1.75 0.1 (0.2) 52X 0.4 2.55 0.1 5.5 0.1 SYMM...
  • Page 70 EXAMPLE BOARD LAYOUT RSH0056E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 3X 0.05 MAX (3.4) ALL AROUND (0.65) 48X (0.2) (1.75) 48X (0.7) SEE SOLDER MASK 4X (0.7) OPTIONS (0.2) TYP 8X (0.2) 1.18 (2.6) (1.45) 1.32 TYP 52X (0.4)
  • Page 71 EXAMPLE STENCIL DESIGN RSH0056E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X (0.7) (1.67) (1.47) 48X (0.2) (0.2) TYP (0.215) 48X (0.7) 8X (0.2) 4X (1.15) 52X (0.4) (1.32) (1.35) (0.775) (0.66) TYP SYMM (6.7) (0.8) (1.35) 8X (1.12)
  • Page 72 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...