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*1 The number of steps may vary depending on the device being used.
Device
Internal device, file register (R0 to R32767)
Direct access input (DX)
Devices other than above
*2 The number of steps may differ, depending on the device or CPU module to be used.
CPU module
Basic model QCPU
High Performance model QCPU
Process CPU
Redundant CPU
Universal model QCPU
LCPU
*3 For the High-speed Universal model QCPU, the number of basic steps is two.
Association instructions
Category
Instruction
symbol
Connection
ANB
ORB
MPS
MRD
MPP
INV
MEP
MEF
EGP
EGF
*1 The number of steps may differ, depending on CPU modules.
CPU module
High Performance model QCPU
Process CPU
Redundant CPU
Universal model QCPU
LCPU
Basic model QCPU
2 INSTRUCTION TABLES
26
2.3 Sequence Instructions
Device
• Internal device, file register (R0 to R32767)
• Direct access input (DX)
Devices other than above
Internal device, file register (R0 to R32767)
• Serial number access format file register (ZR), Extended data register
(D), Extended link register (W), Multiple CPU shared device
(U3En\G10000)
• Direct access input (DX)
Devices other than above
Symbol
ANB
ORB
MPS
MRD
MPP
Vn
Vn
Processing details
• AND between logical blocks
(Series connection between
logical blocks)
• OR between logical blocks
(Series connection between
logical blocks)
• Memory storage of operation
results
• Read of operation results
stored with MPS instruction
• Read and reset of operation
results stored with MPS
instruction
• Inversion of operation result
• Conversion of operation result
to rising edge pulse
• Conversion of operation result
to falling edge pulse
• Conversion of operation result
to rising edge pulse (Stored at
Vn)
• Conversion of operation result
to falling edge pulse (Stored at
Vn)
Number of basic steps
1
2
Number of steps
1
2
3
Number of steps
1
3
Number of basic steps
Number of basic steps +1
Number of basic steps +2
Execution
Number
Subset Reference
condition
of basic
steps
1
1
1
1
1
*1
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