Writing To Host Cpu Shared Memory - Mitsubishi Electric MELSEC-Q/L Programming Manual

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Writing to host CPU shared memory

S(P).TO
Ver.
Ver.
High
Basic
Process
performance
• Q00CPU, Q01CPU: The serial number (first five digits) is "04122" or later.
• High Performance model QCPU: Function version B or later
S.TO
SP.TO
n1:
Start I/O number of the host CPU module
n2:
CPU shared memory address of the write destination host CPU (BIN 16 bits)
 Basic model QCPU: 0 to 511
 High Performance model QCPU, Process CPU, Universal model QCPU: 0 to 4095
n3:
Head number of the devices where data to be written is stored (BIN 16 bits)
n4:
Number of data blocks to be written (BIN 16 bits)
 Basic model QCPU: 1 to 320
 High Performance model QCPU, Process CPU: 1 to 256
 Universal model QCPU: 1 to 2048
(D): Device of the host CPU which is turned ON for one scan by the completion of writing (bits)
Setting
Internal device
data
Bit
n1
n2
n3
n4
(D)
*1 Specified with the upper three digits of the four hexadecimal digits representing the start I/O number.
The value of n1 is specified by the upper three digits of the four hexadecimal digits representing the start I/O number of the
slot where the CPU module has been mounted.
Slot number
CPU slot
Slot 0
Slot 1
Slot 2
9 MULTIPLE CPU DEDICATED INSTRUCTIONS
848
9.1 Writing to the CPU Shared Memory of Host CPU
LCPU
Redundant
Universal
Command
Command
*1
(BIN 16 bits)
R, ZR
Word
Head I/O number
3E00
3E10
3E20
3E30
S.TO
n1
SP.TO
n1
J\
U\G
Bit
Word
n2
n3
n4
D
n2
n3
n4
D
Zn
Constant
K, H
n1
3E0
3E1
3E2
3E3
Others

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