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MELSEC-Q/L
Programming Manual
(Common Instruction)

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Table of Contents

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   Summary of Contents for Mitsubishi Electric MELSEC-Q/L

  • Page 1 MELSEC-Q/L Programming Manual (Common Instruction)
  • Page 3: Safety Precautions

    SAFETY PRECAUTIONS (Read these precautions before using this product.) Before using this product, please read this manual and the related manuals introduced in this manual, and pay full attention to safety to handle the product correctly. Please store this manual in a safe place and make it accessible when required. Always forward a copy of the manual to the end user.
  • Page 4: Introduction

    INTRODUCTION This manual "MELSEC-Q/L Programming Manual (Common Instruction)" describes the common instructions required for programming of the QCPU and LCPU. "Common instructions" are all instructions except for dedicated instructions for intelligent function modules; PID control instructions; process control instruction; SFC instructions; ST instructions; instructions for socket communication features;...
  • Page 5: Table Of Contents

    CONTENTS SAFETY PRECAUTIONS ..............1 CONDITIONS OF USE FOR THE PRODUCT .
  • Page 6 Other instructions ............... . 75 Instructions for Data Link .
  • Page 7 Setting devices (excluding annunciators) ........... . . 158 Resetting devices (excluding annunciators) .
  • Page 8 16-bit BIN data increment, 16-bit BIN data decrement ......... . . 265 32-bit BIN data increment, 32-bit BIN data decrement .
  • Page 9 Ramp signal................345 Pulse density measurement .
  • Page 10 Calculation of averages for 16-bit data, calculation of averages for 32-bit data ......450 Check code ................452 CRC operation.
  • Page 11 Conversion from ASCII to hexadecimal BIN ........... 574 Extracting character string data from the right, extracting character string data from the left .
  • Page 12 File setting for file register ..............679 File setting for comments .
  • Page 13 High-speed block transfer of file register ............812 User message .
  • Page 14: Manuals

    MANUALS To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals. Read other manuals as well when using a different type of CPU module and its functions. Order each manual as needed, referring to the following lists. The numbers in the "CPU module"...
  • Page 15 Describes the general concept, specifications, and part names and settings for MELSECNET Reference Manual () and MELSECNET/B. <IB-66350> MELSEC-Q/L Ethernet Interface Module User's Manual E-mail function, programmable controller CPU status monitoring function, communication via (Application) CC-Link IE Field Network, CC-Link IE Controller Network, MELSECNET/H, or MELSECNET/ <SH-080010>...
  • Page 16: Terms

    TERMS This manual uses the generic names and abbreviations shown below to refer to Q/L series CPU modules, unless otherwise specified.  indicates a part of the model or version. Term Description A5B A generic term for the power source-free type A52B, A55B, and A58B extension base unit on which the A Series I/O module and special function module can be mounted A6B A generic term for the A62B, A65B, and A68B extension base unit on which the A Series I/O module and special...
  • Page 17 Term Description QnPHCPU A generic term for Q02PHCPU, Q06PHCPU, Q12PHCPU and Q25PHCPU QnPRHCPU A generic term for Q12PRHCPU and Q25PRHCPU QnU(D)(H)CPU A generic term for Q02UCPU, Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU, Q20UDHCPU and Q26UDHCPU QnUCPU A generic term for Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU, Q03UDVCPU, Q03UDECPU, Q04UDHCPU, Q04UDVCPU, Q04UDEHCPU, Q06UDHCPU, Q06UDVCPU, Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU, Q13UDVCPU, Q13UDEHCPU, Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU, Q26UDVCPU, Q26UDEHCPU, Q50UDEHCPU and Q100UDEHCPU...
  • Page 18: Chapter 1 General Description

     MELSEC-L CPU Module User's Manual (Function Explanation, Program Fundamentals) Basic model QCPU Qn(H)/QnPH/ QnPRHCPU Describes the functions User's Manual and devices of the CPU (Function Explanation, module, and programming. Program Fundamentals) This manual MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L Programming QnA Programming QnA Programming Programming Programming Manual (Common Manual...
  • Page 19 High Performance model QCPU Qn(H)/QnPH/ QnPRHCPU User's Manual Describes the functions (Function Explanation, and devices of the CPU Program module, and programming. Fundamentals) This manual MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L Programming QnA Programming QnA Programming Programming Programming Manual (Common Manual...
  • Page 20 Redundant CPU Qn(H)/QnPH/ Describes the functions and QnPRHCPU devices of the CPU module, User's Manual and programming. (Function Explanation, Program Fundamentals) This manual MELSEC-Q/L MELSEC-Q MELSEC-Q/L/QnA MELSEC-Q/L MELSEC-Q/L Programming Manual Programming Manual Programming Manual Programming Manual Programming/ (Common Instruction) (SFC)
  • Page 21 Universal model QCPU QnUCPU Describes the functions and User's Manual devices of the CPU module, and programming. (Function Explanation, Program Fundamentals) This manual MELSEC-Q/L MELSEC-Q/L/QnA MELSEC-Q/L MELSEC-Q/L MELSEC-Q Programming Manual Programming/ Programming Manual Programming Manual Programming Manual (Common Instruction) (SFC)
  • Page 22 LCPU MELSEC-L Describes the functions and CPU Module devices of the CPU module, User's Manual and programming. (Function Explanation, Program Fundamentals) This manual MELSEC-Q/L MELSEC-Q/L/QnA MELSEC-Q/L/QnA MELSEC-Q/L MELSEC-Q/L Programming Manual Programming Manual Programming Manual Programming Manual Programming Manual (Common Instruction)
  • Page 23: Chapter 2 Instruction Tables

    INSTRUCTION TABLES Types of Instructions The major types of CPU module instructions consist of sequence instructions, basic instructions, application instructions, data link instructions, QCPU instructions and redundant system instructions. These types of instructions are listed in the following Table. Types of instructions Description Reference Sequence...
  • Page 24 Types of instructions Description Reference Application Logical operation instruction Logical operations such as logical sum, logical product, etc. Page 355 instruction APPLICATION Rotation instruction Rotation of designated data INSTRUCTIONS Shift instruction Shift of designated data Bit processing instruction Bit set and reset, bit test, batch reset of bit devices Data processing instruction 16-bit data searches, data processing such as decoding and encoding Structure creation instruction...
  • Page 25: How To Read Instruction Tables

    How to Read Instruction Tables The instruction tables found from Page 25 Sequence Instructions to Page 79 Redundant System Instructions (For Redundant CPU) have been made according to the following format: Ò Ó Ô Õ Ö × Ø Ù  Classifies instructions according to their application. ...
  • Page 26  Indicates the type of processing that is performed by individual instructions. (D)+(S) (D+1, D) +(S+1, S) (D +1,D) 16 bits 16 bits Indicates 16 bits. Indicates 32 bits. Upper 16 bits Lower 16 bits  Indicates execution conditions for individual instructions. Execution condition Non-conditional Executed at ON...
  • Page 27 Sequence Instructions Contact instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Contact • Starts logic operation (Starts A contact logic operation) ● Page 131 • Starts logical NOT operation (Starts B contact logic operation) •...
  • Page 28: Association Instructions

    *1 The number of steps may vary depending on the device being used. Device Number of steps Internal device, file register (R0 to R32767) Direct access input (DX) Devices other than above *2 The number of steps may differ, depending on the device or CPU module to be used. CPU module Device Number of steps...
  • Page 29: Output Instructions

    Output instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Output • Device output  Page 148 Page 150 Page 154 Page 156  • Sets device Page 158 Page 162 Annunciator (F)  •...
  • Page 30: Termination Instructions

    Termination instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Termination FEND • Termination of main Page 177 FEND program • Termination of sequence Page 179 program *1 For the High-speed Universal model QCPU, the number of basic steps is two. Other instructions Category Instruction...
  • Page 31 Basic Instructions Comparison operation instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps BIN 16-bit • Conductive status when (S1) ● Page 187 S1 S2 data = (S2) comparisons • Non-conductive status when AND= S1 S2 (S1) ...
  • Page 32 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps BIN 32-bit LDD= • Conductive status when ● Page 189 S1 S2 data (S1+1, S1) = (S2+1, S2) comparisons • Non-Conductive status when ANDD= S1 S2 (S1+1, S1) ...
  • Page 33 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Floating LDE= • Conductive status when Page 191 S1 S2 decimal (S1+1, S1) = (S2+1, S2) point data • Non-Conductive status when ANDE= S1 S2 (S1+1, S1) ...
  • Page 34 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Floating LDED= • Conductive status when Page 193 S1 S2 decimal (S1+3, S1+2, S1+1, S1) = point data (S2+3, S2+2, S2+1, S2) ANDED= S1 S2 comparisons •...
  • Page 35 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Character LD$= • Compares character string Page 196 S1 S2 string data S1 and character string S2 comparisons one character at a time. AND$= S1 S2 •...
  • Page 36 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  BIN 16-bit BKCMP= • This instruction compares Page 199 BKCMP S1 S2 D Block data BIN 16-bit data stored in n- comparisons point devices starting from BKCMP<>...
  • Page 37 *1 The number of steps may differ, depending on the device or CPU module to be used. CPU module Device Number of Remark steps High Performance model QCPU • Word device: Internal device (except for file register When using a High Performance model Process CPU QCPU, Process CPU or Redundant CPU, Redundant CPU...
  • Page 38: Arithmetic Operation Instruction

    Arithmetic operation instruction Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● BIN 16-bit • D+(S)(D) Page 220 addition and subtraction operations ● • (S1)+(S2)(D) Page 222 S1 S2 D S1 S2 D ● •...
  • Page 39 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps BCD 4-digit • (D)+(S)(D) ● Page 232 addition and subtraction operations  • (S1)+(S2)(D) Page 234 S1 S2 D S1 S2 D • (D)-(S)(D) ● Page 232 ...
  • Page 40 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● Floating • (D+1, D)+(S+1, S)(D+1, D) Page 244 decimal point data addition and subtraction • (S1+1, S1)+(S2+1, S2)(D+1, ● Page 246 operations S1 S2 D (single precision) S1 S2 D...
  • Page 41 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  BIN 16-bit • This instruction adds BIN 16-bit Page 256 S1 S2 data block data stored in n-point devices addition and starting from the device BK+P BK+P S1 S2...
  • Page 42 *1 The number of steps may differ, depending on the device or CPU module to be used. CPU module Device Number of Remark steps High Performance model QCPU • Word device: Internal device (except for file register When using a High Performance model Process CPU QCPU, Process CPU or Redundant CPU, Redundant CPU...
  • Page 43: Data Conversion Instructions

    Data conversion instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● Page 269 BCD conversions conversions BCDP BIN (0 to 9999) BCDP DBCD ● BCD conversions DBCD (S+1, S) (D+1, D) DBCDP BIN (0 to 99999999) DBCDP ●...
  • Page 44 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps BIN 16-bit   Page 281 Conversion 32-bit (D+1, D) conversions BIN (-32768 to 32767) DBLP DBLP  WORD Page 282 Conversion WORD (S+1, S) BIN (-32768 to 32767) WORDP WORDP BIN ...
  • Page 45 *1 The number of basic steps is two for the Universal model QCPU and LCPU. *2 The subset is effective only with Universal model QCPU and LCPU. *3 For the High-speed Universal model QCPU, the number of basic steps is two. 2 INSTRUCTION TABLES 2.4 Basic Instructions...
  • Page 46 Data transfer instruction Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● 16-bit data • (S)(D) Page 297 transfer MOVP MOVP ● 32-bit data DMOV • (S+1, S)(D+1, D) DMOV transfer DMOVP DMOVP ● Floating EMOV Page 299...
  • Page 47 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Exchange SWAP Page 318 SWAP b8 b7 of upper 8 bits 8 bits and lower SWAPP SWAPP bytes b8 b7 8 bits 8 bits Shift SMOV ...
  • Page 48: Program Branch Instructions

    Program branch instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● Jump • Jumps to Pn when input Page 321 conditions are met. ● • Jumps to Pn from the scan after the meeting of input condition.
  • Page 49: Other Convenient Instructions

    Other convenient instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Up/Down UDCNT1  Page 334 UDCNT1 (S)+0 counter (S)+1 Down Present 1 2 3 4 6 7 6 5 3 2 1 0 -1 -2 -3 -2 -1 0 value contact ...
  • Page 50 Application Instructions Logical operation instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Logical WAND • (D)(S)(D) ● Page 356 WAND product WANDP WANDP WAND • (S1)(S2)(D) ● Page 358 WAND S1 S2 D WANDP WANDP S1 S2 D...
  • Page 51 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Exclusive WXOR • (D)(S)(D) ● Page 369 WXOR WXORP WXORP ● WXOR • (S1)(S2)(D) Page 371 WXOR S1 S2 D WXORP WXORP S1 S2 D DXOR •...
  • Page 52 *1 The number of basic steps is three for the Universal model QCPU and LCPU. *2 The number of steps may differ, depending on the device or CPU module to be used. CPU module Device Number of Remark steps High Performance model QCPU •...
  • Page 53: Rotation Instructions

    Rotation instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Right ● Page 381 SM700 rotation of 16-bit data RORP RORP Right rotation by n bits Carry flag ● SM700 RCRP RCRP Right rotation by n bits Carry flag Left rotation ●...
  • Page 54 Shift instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● n-bit shift of Page 391 16-bit data Carry flag SFRP SFRP b0 SM700 0 to 0 ● Carry flag SFLP SM700 SFLP 0 to 0 1-bit shift of BSFR ...
  • Page 55 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Bit shift SFTR Page 404 SFTR S D n1 right/shift left SFTRP SFTRP S D n1 SFTL  Page 406 SFTL S D n1 SFTLP SFTLP S D n1 ...
  • Page 56: Bit Processing Instructions

    Bit processing instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ● Bit set/reset BSET Page 412 BSET BSETP BSETP BRST ● BRST BRSTP BRSTP  Bit tests TEST Page 414 (S1) TEST S1 S2 D TESTP TESTP S1 S2 D...
  • Page 57: Data Processing Instructions

    Data processing instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Data  Page 418 (S2) S1 S2 D (S1) searches SERP SERP S1 S2 D (D): Match No. (D + 1): Number of matches DSER ...
  • Page 58 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Separating • Separates 16-bit data Page 429 and linking designated by (S) into 4-bit units, and stores at the lower DISP DISP 4 bits of n points from (D). (n4) ...
  • Page 59 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Sort SORT • Sorts data of n points from Page 444 S1 n SORT S2 D1 device designated by (S1) in 16-bit units. (n  (n-1)/2 scans •...
  • Page 60: Structure Creation Instructions

    Structure creation instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Number of • Executes n times between Page 457 repeats the [FOR] and [NEXT]. NEXT  NEXT  BREAK • Forcibly ends the Page 460 BREAK execution of the [FOR] to...
  • Page 61 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Select • Performs auto refresh of Page 487 refresh intelligent function modules, auto refresh of link refresh, and communications with peripherals. • Performs auto refresh of ...
  • Page 62: Data Table Operation Instructions

    Data table operation instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Data table FIFW Page 498 Pointer Pointer + 1 FIFW processing FIFWP FIFWP Device at pointer + 1  FIFR Page 500 (S) Pointer Pointer - 1 FIFR...
  • Page 63: Display Instructions

    Display instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps ASCII print • Outputs ASCII code from  Page 512 When SM701 is OFF device designated by (S) to 00H to output module. • Outputs ASCII code of 8 When SM701 is ON points (16 characters) from device designated by (S) to...
  • Page 64: Character String Processing Instructions

    Character string processing instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps BIN   BINDA • Converts 1-word BIN value Page 528 BINDA Decimal designated by (S) to a 5-digit, ASCII decimal ASCII value, and stores BINDAP it at the word device designated BINDAP...
  • Page 65 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Decimal DABCD • Converts a 4-digit, decimal Page 543 DABCD ASCII  ASCII value designated by (S) to a 1-word BCD value, and stores DABCDP it at a word device number DABCDP designated by (D).
  • Page 66 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Hexadecimal • Converts the 1-word BIN value Page 572 BIN  ASCII at the device numbers designated by (S) to ASCP hexadecimal ASCII, and stores ASCP n characters of them at the device numbers designated by...
  • Page 67: Special Function Instructions

    Special function instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Trigonometric • Sin(S+1, S)(D+1, D)  Page 594 functions (Floating-point SINP single- SINP precision)  • Cos(S+1, S)(D+1, D) Page 598 COSP COSP ...
  • Page 68 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps Angles   • (S+1, S)(D+1, D) Page 618 Radians Conversion from angles to radians conversion RADP RADP RADD • (S+3, S+2, S+1, S)(D+3, D+2,  Page 620 RADD D+1, D)
  • Page 69 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Random • Generates a random number (from 0 Page 646 number to less than 32767) and stores it at generation the device designated by (D). RNDP RNDP Random...
  • Page 70: Data Control Instructions

    Data control instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Page 662 Upper and LIMIT • When (S3) < (S1), a value of (S1) LIMIT S1 S2 lower limit is stored at (D). •...
  • Page 71 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  X or Y SCL2 • Executes scaling for the scaling Page 674 SCL2 S1 S2 D coordinate conversion data (16-bit data units) data specified by (S2) with the input SCL2P SCL2P S1 S2 D...
  • Page 72: Clock Instructions

    Clock instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Read/write DATERD Page 683 (Clock elements) (D) +0 Year DATERD D clock data Month Hour DATERDP Minute DATERDP D Sec. Day of the week ...
  • Page 73 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Date LDDT= Page 697 S1 S2 n Year Year Comparison comparison operation Month Month result ANDDT= S1 S2 ORDT= S1 S2  LDDT<> S1 S2 n Year Year Comparison...
  • Page 74 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Clock LDTM= Page 701 S1 S2 n Hour Hour comparison Comparison operation Minute Minute result ANDTM= Second Second S1 S2 ORTM= S1 S2 LDTM<>  S1 S2 n Hour Hour...
  • Page 75: Expansion Clock Instructions

    Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Clock data TZCP Page 707 TZCP S1 S2 S3 Hour Hour band turns on. min. min. comparison Sec. Sec. TZCPP TZCPP S1 S2 S3 Hour Hour Hour min.
  • Page 76: Program Control Instructions

    Program control instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Program PSTOP • Places designated program in Page 719 PSTOP File name control standby status. instructions PSTOPP PSTOPP File name POFF • Turns OUT instruction coil of ...
  • Page 77: Other Instructions

    Other instructions Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps WDT reset • Resets watchdog timer during  Page 752 sequence program. WDTP WDTP  Timing DUTY Page 754 DUTY n1 n2 D clock n1 scans n2 scans SM420 to SM424, SM430 to SM434...
  • Page 78 Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Writing data SP.FWRITE • Writes data to the designated file. Page 779 SP.FWRITE S0 D0 S1 S2 to the designated file Reading SP.FREAD • Reads data from the designated ...
  • Page 79: Instructions For Data Link

    Instructions for Data Link Instructions for network refresh Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Link S.ZCOM • Refreshes the designated Page 820 S.ZCOM instruction: network. Network SP.ZCOM refresh SP.ZCOM Jn S.ZCOM S.ZCOM SP.ZCOM SP.ZCOM Un...
  • Page 80: Multiple Cpu Dedicated Instruction

    Multiple CPU Dedicated Instruction Instructions for writing to the CPU shared memory of host CPU Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Write to S.TO • Writes device data of the host Page 848 S.TO host CPU...
  • Page 81: Multiple Cpu High-speed Transmission Dedicated Instruction

    Multiple CPU High-speed Transmission Dedicated Instruction Instructions for multiple CPU high-speed transmission Category Instruction Symbol Processing details Execution Number Subset Reference symbol condition of basic steps  Writing D.DDWR • In multiple CPU system, data Page 872 D.DDWR devices to stored in a device specified by another host CPU ((S2)) or later is...
  • Page 82: Chapter 3 Configuration Of Instructions

    CONFIGURATION OF INSTRUCTIONS Configuration of Instructions Most CPU module instructions consist of an instruction part and a device part. Each part is used for the following purpose: • Instruction part: indicates the function of the instruction. • Device part: indicates the data that is to be used with the instruction. The device part consists of source data, destination data, and number of devices.
  • Page 83: Designating Data

    Designating Data The following six types of data can be used with CPU module instructions. Data that can be handled Bit data by CPU module Numeric data Integer data Word data Double-word data Real number Single-precision (floating point) data floating point data Double-precision floating point data Character string data...
  • Page 84: Using Bit Data

    Using bit data Bit data is data used in one-bit units, such as for contacts or coils. "Bit devices" and "Bit designated word devices" can be used as bit data. When using bit devices Bit devices are designated in one-point units. Designation of 1 point of bit device M0 Designation of 1 point...
  • Page 85: Using Word (16 Bits) Data

    Using word (16 bits) data Word data is 16-bit numeric data used by basic instructions and application instructions. The following two types of word data can be used with CPU module: • Decimal constants: K-32768 to K32767 • Hexadecimal constants: H0000 to HFFFF Word devices and bit devices designated by digit can be used as word data.
  • Page 86 In cases where digit designation is made at the destination (D), the number of points designated are used as the destination. Bit devices below the number of points designated as digits do not change. Ladder example Processing • When source (S) data is a numerical value X010 H1234 0 0 0 1 1 0 1 0 0...
  • Page 87: Using Double Word (32 Bits) Data

    Using double word (32 bits) data Double word data is 32-bit numerical data used by basic instructions and application instructions. The two types of double word data that can be dealt with by CPU module are as follows: • Decimal constants: K-2147483648 to K2147483647 •...
  • Page 88 When destination (D) data is a word device, the word device for the destination becomes 0 following the bit designated by digit designation at the source. Ladder example Processing • With 32-bit instructions K1X0 X3 X2 X1 X0 DMOV K1X0 Filled with 0s 0 0 0 0 0 0 0 0 0 0 X2 X1 X0...
  • Page 89: Using Single/double-precision Real Number Data

    Using single/double-precision real number data Real number data is floating decimal point data used with basic instructions and application instructions. Only word devices are capable of storing real number data. Single-precision real number data (single-precision floating-point data) Instructions which deal with single-precision floating-point data designate devices which are used for the lower 16 bits of data. Single-precision floating-point data are stored in the 32 bits which make up (designated device number) and (designated device number + 1).
  • Page 90 Double-precision real number data (double-precision floating-point data) Instructions which deal with double-precision floating-point data designate devices which are used for the lower 16 bits of data. Double-precision floating-point data are stored in the 64 bits which make up (designated device number) to (designated device number + 3).
  • Page 91 Precautions Precautions when an input value of a single/double-precision real number is set using a programming tool are shown below. ■Single-precision real number Because single-precision real number data are processed as the 32-bit single-precision in a programming tool, the number of significant digits becomes approximately 7.
  • Page 92 The CPU module floating decimal point data can be monitored using the monitoring function of a programming tool. When floating-point data is used to express 0, all data in the following range are turned to 0. • Single-precision floating-point data: b0 to b31 •...
  • Page 93: Using Character String Data

    Using character string data Character string data is character data used by basic instructions and application instructions. The target ranges from the designated character to the NULL code (00H) that indicates the end of the character string. When designated character is the NULL code One word is used to store the NULL code.
  • Page 94: Indexing

    Indexing Overview of indexing Indexing is an indirect setting made by using an index register. When an Indexing is used in a sequence program, the device to be used will become the device number specified directly plus the contents of the index register. For example, if D2Z2 has been specified, the specified device is calculated as follows: D(2+3) = D5 and the content of Z2 is 3 become the specified device.
  • Page 95 *1 SFC transfer devices and SFC block devices are devices for SFC use. Refer to the manual below for how to use these devices.  MELSEC-Q/L/QnA Programming Manual (SFC) *2 For the High-speed Universal model QCPU, the SFC block device (BL) and step relay (S) can be modified using indices within the following range.
  • Page 96 ■A case where indexing has been performed, and the actual process device (Z0 =20, Z1 = -5) Ladder example Actual process device MOV K2X64 K1M33 MOV K20 Description K2X(50 + 14) = K2X64 K2X50Z0 MOV K 5 Converts K20 into a hexadecimal number. K1M38Z1 K1M(38 - 5) = K1M33 MOV K2X50Z0 K1M38Z1...
  • Page 97 Indexing with 32-bit index registers A method of specifying index registers in indexing with 32-bit can be selected from the following two methods. • Specifying the index registers' range used for indexing with 32-bit. • Specifying the 32-bit indexing using "ZZ" specification. *1 The methods applies only to Universal model QCPU (excluding Q00UJCPU) and LCPU.
  • Page 98 • Device that indexing can be used Indexing can be used only for the device shown below. Device Description Serial number access format file register Extended data register (D) Extended link register (W) • Usable range of index registers The following table shows the usable range of index registers for indexing with 32-bit index registers. For indexing with 32-bit index registers, the specified index register (Zn) and the next index register of the specified register (Zn+1) are used.
  • Page 99 ■Example of specifying 32-bit indexing with "ZZ" specification One index register can specify 32-bit indexing by using "ZZ" specification such as "ZR0ZZ4". The 32-bit indexing with "ZZ" specification is as follows. Stores 100000 at Z4 and Z5. DMOVP K100000 Indexing ZR device with 32-bit MOVP K100 ZR0ZZ4...
  • Page 100 • A case where 32-bit indexing used "ZZ" specification has been performed, and the actual process device (Z0 (32-bit) =100000, Z2 (32-bit) = -20) Ladder example Actual process device ZR101000 D10 DMOV K100000 Z0 K-20 Description ZR1000ZZ0 D30Z2 ZR1000ZZ0 ZR(1000+100000)=ZR101000 D30Z2 D(30-20)=D10 •...
  • Page 101 Index modification using extended data register (D) and extended link register (W) Like index modification using data register (D) and link register (W) of internal user device, a device can be specified by index modification within the range of the extended data register (D) and extended link register (W). *1 This applies only to Universal model QCPU (excluding Q00UJCPU) and LCPU.
  • Page 102 ■Index modification where the device number crosses over the boundary among the file register (ZR), extended data register (D), and extended link register (W) Index modification where the device number crosses over the boundary among the file register (ZR), extended data register (D), and extended link register (W) will not cause an error.
  • Page 103 Other index modifications For bit data, device numbers can be index modified when performing digit designation. However, Indexing is not possible by digit designation. BIN K4X0Z2 Setting is possible since this indicates Indexing for device number. If Z2=3, then (X0+3)=X3 BIN K4Z3X0 Setting is not possible since this indicates Indexing by digit designation.
  • Page 104 Cautions ■Performing indexing between the FOR and NEXT instructions Pulses can be output between the FOR and NEXT instructions by use of the edge relay (V). However, pulse output using the PLS/PLF/pulse (P) instruction is not allowed. When edge relay is used When edge relay is not used M0Z1 provides normal pulse output.
  • Page 105 ■Device range check during indexing • Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU Device range checks are not conducted during indexing. Therefore, when the data after index modification exceed the user specified device range, the data is read by another device or written to another device without causing an error.
  • Page 106 ■Changing indexing with 16-bit index register for indexing with 32-bit index register For changing indexing with 16-bit index register for indexing with 32-bit index register, check if the program has enough spaces for indexing. For indexing with 32-bit index registers, the specified index register (Zn) and the next index register of the specified register (Zn+1) are used.
  • Page 107: Indirect Specification

    Indirect Specification Indirect Specification Indirect specification is a method that specifies address of the device to be used in a sequence program using two word devices (two points of word device). Use indirect specification as index modification when the index register is insufficient. ADRSET D100 Store the address of D100 in D0 and D1.
  • Page 108 Precautions ■Address for indirect specification The address for indirect specification uses two words. Therefore, to substitute indirect specification for index modification, the addition/subtraction of 32-bit data is required. The following is the ladder used for the address addition/subtraction of the device stored in D1 and D0 for indirect specification.
  • Page 109 ■Indirect specification and index modification When a device is specified by both indirect specification and index modification, index modification is executed first and then the device is specified by indirect specification. Store K5 in the index register Z2. ADRSET D0 D100Z2 Store the address of D0 in D105 and D106 (D(100) + 5) = D105).
  • Page 110: Reducing Instruction Processing Time

    Reducing Instruction Processing Time Subset processing Subset processing is used to place limits on bit devices used by basic instructions and application instructions in order to increase processing speed. However, the instruction symbol does not change. To shorten scans, run instructions under the conditions indicated below. Conditions which each device must meet for subset processing ■When using word data Device...
  • Page 111: Operation Processing With Standard Device Registers (z) (universal Model Qcpu And Lcpu Only)

    Instructions for which subset processing can be used Types of instructions Instruction symbol Contact instructions LD, LDI, AND, ANI, OR, ORI, LDP, LDF, ANDP, ANDF, ORP, ORF, LDPI, ANDPI, ANDFI, ORPI, ORFI Output instructions OUT, SET, RST Comparison operation instructions =, <>, <, <=, >, >=, D=, D<>, D<, D<=, D>, D>= Arithmetic operation +, -, *, /, INC, DEC, D+, D-, D*, D/, DINC, DDEC, B+, B-, B*, B/, E+, E-, E*, E/...
  • Page 112: Cautions On Programming (operation Errors)

    Cautions on Programming (Operation Errors) Operation errors are returned in the following cases when executing basic instructions and application instructions with CPU module: • An error listed on the explanatory page for the individual instruction occurred. • When an intelligent function module device is used, no intelligent function module is installed at the specified I/O number position.
  • Page 113 Device range check Device range checks for the devices used by basic instructions and application instructions in CPU module are as indicated below: ■Instructions for specified each device, including MOV and DMOV • For the Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU. The device range is not checked.
  • Page 114 ■Instructions for a block of devices, including BMOV and FMOV • For the Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU. The device range is checked. When the device number is outside the device range, an operation error occurs. For example, when 12K points are assigned to a data register, an error occurs if the device number of the data register exceeds D12287.
  • Page 115 ■Character string data • For the Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU. Because all character string data is of variable length, device range checks are performed. When the device number is outside the device range, an operation error occurs. For example, in a case where the data register has been allocated 12K points, there will be an error if it exceeds D12287.
  • Page 116 ■Precautions for using the extended data register (D) or extended link register (W) With the following specification methods, data cannot be specified crossing over the boundary of the internal user device and extended data register (D) or extended link register (W). Doing so causes "OPERATION ERROR" (error code: 4101). *1 Universal model QCPU (models other than Q00UJCPU) and LCPU are applicable.
  • Page 117 ■Precautions when using Universal model QCPU/LCPU For the Universal model QCPU and LCPU, an error occurs if any of the following accesses is performed using the following instructions and data. (Error code: 4101) Instructions and data • Instructions for specified each device, including MOV and DMOV •...
  • Page 118 Device data check Device data checks for the devices used by basic instructions and application instructions in CPU module are as indicated below: ■When using BIN data No error is returned even if the operation results in overflow or underflow. The carry flag (SM700) does not go on at such times, either.
  • Page 119: Conditions For Execution Of Instructions

    Conditions for Execution of Instructions The following four types of execution conditions exist for the execution of CPU module sequence instructions, basic instructions, and application instructions: Execution condition Description Non-conditional execution  An instruction is always executed regardless of whether the precondition of the instruction is on or off. When the precondition is off, the instruction performs off processing.
  • Page 120: Counting Step Number

    Counting Step Number The number of steps in CPU module sequence instructions, basic instructions, and application instructions differs depending on whether indirect setting of the device used is possible or not. Counting the number of basic steps The basic number of steps for basic instructions and application instructions is calculated by adding the device number and 1. For example, the "+ instruction"...
  • Page 121 Instruction symbol Devices with additional steps Added steps Number of basic (number of steps instruction steps) Serial number access format file register, Extended data 1(2) register (D), Extended link register (W) Multiple CPU shared device Timer/Counter 3(4) Serial number access format file register, Extended data 1(2) register (D), Extended link register (W) Multiple CPU shared device...
  • Page 122 Instruction symbol Devices with additional steps Added steps Number of basic (number of steps instruction steps) DMOV, DMOVP, EMOV, EMOVP Serial number access format file register, Extended data register (D), Extended link register (W) Multiple CPU shared device Decimal constant, hexadecimal constant, real constant BCD, BCDP, BIN, BINP, FLT, FLTP, CML, CMLP Serial number access format file register, Extended data (S): 1, (D): 2...
  • Page 123 The following table shows steps depending on the devices. Devices with additional steps Added steps Example Intelligent function module device MOV U4\G10 D0 Multiple CPU shared device MOV U3E1\G10000 D0 Link direct device MOV J3\B20 D0 Index register / standard device register MOV Z0 D0 Serial number access format file register MOV ZR123 D0...
  • Page 124: Operation When The Out, Set/rst, Or Pls/plf Instructions Use The Same Device

    Operation When the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device The following describes the operation for executing multiple instructions of the OUT, SET/RST, or PLS/PLF that use the same device in one scan. OUT instructions using the same device Do not program more than one OUT instruction using the same device in one scan.
  • Page 125 SET/RST instructions using the same device • The SET instruction turns ON the specified device when the execution command is ON and performs nothing when the execution command is OFF. For this reason, when the SET instructions using the same device are executed two or more times in one scan, the specified device will be ON if any one of the execution commands is ON.
  • Page 126 PLS instructions using the same device The PLS instruction turns ON the specified device when the execution command is turned ON from OFF. It turns OFF the device at any other time (OFF to OFF, ON to ON, or ON to OFF). If two or more PLS instructions using the same device are executed in one scan, each instruction turns ON the device when the corresponding execution command is turned ON from OFF and turns OFF the device in other cases.
  • Page 127 PLF instructions using the same device The PLF instruction turns ON the specified device when the execution command is turned OFF from ON. It turns OFF the device at any other time (OFF to OFF, OFF to ON, or ON to ON). If two or more PLF instructions using the same device are executed in one scan, each instruction turns ON the device when the corresponding execution command is turned OFF from ON and turns OFF the device in other cases.
  • Page 128: Precautions For Use Of File Registers

    3.10 Precautions for Use of File Registers This section explains the precautions for use of the file registers in the QCPU and LCPU. CPU modules that cannot use file registers The Q00JCPU and Q00UJCPU cannot use the file registers. When using the file registers, use the CPU module of other than the Q00JCPU and Q00UJCPU.
  • Page 129 File register specifying method There are the block switching method and serial number access method to specify the file registers. ■Block switching method In the block switching method, specify the number of used file register points in units of 32K points (one block). For file registers of 32K points or more, specify the file registers by switching the block No.
  • Page 130 ■Restrictions The restrictions when specifying file registers to refresh devices are as follows. • On QCPU, Refresh cannot be performed correctly if the use of file register which has the same name as the program is specified by the PLC parameter. When the file register which has the same name as the program is used, refresh is performed to the data of the file register having the same name as the program that is set at the last number in the [Program] tab page of PLC parameter.
  • Page 131: Chapter 4 How To Read Instructions

    HOW TO READ INSTRUCTIONS The description of instructions that are contained in the following chapters are presented in the following format. Ò Ó Ô Õ Ö × Ø Ù  Code used to write instruction (instruction symbol).  Shows if instructions are enabled or disabled for each CPU module type. Icon Description Basic model...
  • Page 132  Indicates ladder mode expressions and execution conditions for instructions. Execution condition Non-conditional Executed at ON Executed at the Executed at OFF Executed at the execution rising edge falling edge Code recorded on No symbol recorded description page For execution conditions, refer to Page 117 Conditions for Execution of Instructions. ...
  • Page 133: Sequence Instructions

    Internal device R, ZR J\ U\G Constant Others data Word Word    When BL, S, TR, BL\S, or BL\TR is used, refer to the SFC control instructions in the MELSEC-Q/L/QnA Programming Manual (SFC). 5 SEQUENCE INSTRUCTIONS 5.1 Contact Instructions...
  • Page 134 Processing details ■LD, LDI • LD is the A contact operation start instruction, and LDI is the B contact operation start instruction. They read ON/OFF information from the designated device , and use that as an operation result. *1 When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of the designated bit. ■AND, ANI •...
  • Page 135 • A program linking contacts using the ANB and ORB instructions. [Ladder Mode] [List Mode] Instruction Device Step Bit designated for word device • A parallel program with the OUT instruction. [Ladder Mode] [List Mode] Step Instruction Device 5 SEQUENCE INSTRUCTIONS 5.1 Contact Instructions...
  • Page 136: Pulse Operation Start, Pulse Series Connection, Pulse Parallel Connection

    Pulse operation start, pulse series connection, pulse parallel connection LDP, LDF, ANDP, ANDF, ORP, ORF High Basic Process Redundant Universal LCPU performance Bit device number / Word device bit designation X1/D0.1 X1/D0.1 X2/D0.2 ANDP X2/D0.2 ANDF X3/D0.3 X3/D0.3 (S): Devices used as contacts (bits) Setting Internal device R, ZR...
  • Page 137 ■ANDP, ANDF • ANDP is a rising edge pulse series connection instruction, and ANDF is a falling edge pulse series connection instruction. They perform an AND operation with the operation result to that point, and take the resulting value as the operation result. The ON/OFF data used by ANDP and ANDF are indicated in the table below: Device specified in ANDP or ANDF ANDP state...
  • Page 138: Pulse Not Operation Start, Pulse Not Series Connection, Pulse Not Parallel Connection

    Pulse NOT operation start, pulse NOT series connection, pulse NOT parallel connection LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported Bit device number / Word device bit designation X1/D0.1...
  • Page 139 ■ANDPI, ANDFI • ANDPI is a rising edge pulse NOT series connection, and ANDFI is a falling pulse NOT series connection. ANDPI and ANDFI execute an AND operation with the previous operation result, and take the resulting value as the operation result. The on or off data used by ANDPI and ANDFI are indicated in the table below.
  • Page 140: Association Instructions

    Association Instructions Ladder block series connection, ladder block parallel connection ANB, ORB High Basic Process LCPU Redundant Universal performance Block A Block B Block A Block B For parallel connection of 1 contact, OR or ORI is used. Setting Internal device R, ZR J\...
  • Page 141 Program example • A program using the ANB and ORB instructions. [Ladder Mode] [List Mode] Step Instruction Device 5 SEQUENCE INSTRUCTIONS 5.2 Association Instructions...
  • Page 142: Operation Results Push, Operation Results Read, Operation Results Pop

    Operation results push, operation results read, operation results MPS, MRD, MPP High Basic Process Redundant Universal LCPU performance In the ladder display, MPS, MRD and MPP are not displayed. Command Command Command Command Setting Internal device R, ZR J\ U\G Constant Others data...
  • Page 143 Operation error • There is no operation error in the MPS, MRD, or MPP instruction. Program example • A program using the MPS, MRD, and MPP instructions. [Ladder Mode] [List Mode] Step Instruction Device 5 SEQUENCE INSTRUCTIONS 5.2 Association Instructions...
  • Page 144 • A program using the MPS and MPP instructions successively. [Ladder Mode] [List Mode] Instruction Device Step 5 SEQUENCE INSTRUCTIONS 5.2 Association Instructions...
  • Page 145: Operation Results Inversion

    Operation results inversion High Basic Process LCPU Redundant Universal performance Command Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Inverts the operation result immediately prior to the INV instruction. Operation result immediately prior to the INV instruction Operation result following the execution of the INV instruction Operation error •...
  • Page 146 • The INV instruction operates based on the results of calculation made until the INV instruction is given. Accordingly, use it in the same position as that of the AND instruction. The INV instruction cannot be used at the LD and OR positions. •...
  • Page 147: Operation Results Conversion

    Operation results conversion MEP, MEF High Basic Process LCPU Redundant Universal performance Command Command Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details ■MEP • If operation results up to the MEP instruction are rising edge (from OFF to ON), goes ON (continuity status). If operation results up to the MEP instruction are anything other than rising edge, goes OFF (non-continuity status).
  • Page 148: Pulse Conversion Of Edge Relay Operation Results

    Pulse conversion of edge relay operation results EGP, EGF High Basic Process Redundant Universal LCPU performance Command Command (D): Edge relay number where operation results are stored (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word ...
  • Page 149 Program example • A program using the EGP instruction in the subroutine program using the EGD instruction [Ladder Mode] [List Mode] Instruction Device Step [Operation] END processing Turns OFF as X0 remains ON. Turns ON at the leading Turns OFF as X1 remains ON. edge of X0.
  • Page 150: Output Instructions

    Output Instructions Out (excluding timers, counters, and annunciators) High Basic Process LCPU Redundant Universal performance Bit device number (D) Command Word device bit designation (D) Command D0.5 (D): Number of the device to be turned ON and OFF (bits) Setting Internal device R, ZR J\...
  • Page 151 Program example • When using bit devices [Ladder Mode] [List Mode] Instruction Device Step • When bit designation has been made for word device [Ladder Mode] [List Mode] Step Instruction Device 5 SEQUENCE INSTRUCTIONS 5.3 Output Instructions...
  • Page 152: Low-speed Timer, High-speed Timer, Low-speed Retentive Timer, High-speed Retentive Timer

    Low-speed timer, high-speed timer, low-speed retentive timer, high-speed retentive timer OUT T, OUTH T, OUT ST, OUTH ST High Basic Process Redundant Universal LCPU performance Command Set value Setting in the range from 1 to 32767 is valid. OUT T Timer number (D) (Low-speed timer) Command...
  • Page 153 Processing details • When the operation results up to the OUT instruction are ON, the timer coil goes ON and the timer counts up to the value that has been set; when the time up status (total numeric value is equal to or greater than the setting value), the contact responds as follows: •...
  • Page 154 Precautions When creating a program in which the operation of the timer contact triggers the operation of another timer, create the program for the timer that operates later first. In the following cases, all timers go ON at the same scan if the program is created in the order the timers operate. •...
  • Page 155 Program example • The following program turns Y10 and Y14 ON 10 seconds after X0 has gone ON. [Ladder Mode] [List Mode] Instruction Step Device (1) The setting value of the low-speed timer indicates its default time limit (100ms). • The following program uses the BCD data at X10 to X1F as the timer's set value. [Ladder Mode] Converts the BCD data at X10 to X1F to BIN and stores the converted value at D10.
  • Page 156: Counter

    Counter OUT C High Basic Process Redundant Universal LCPU performance Set value Command Setting in the range from 1 to 32767 is valid. Counter number (D) OUT C Set value Command Data register value in the range from 1 to 32767 is valid. Counter number (D) (D): Counter number (bits) Setting value Counter setting value (BIN 16 bits...
  • Page 157 Program example • The following program turns Y30 ON after X0 has gone ON 10 times, and resets the counter when X1 goes ON. [Ladder Mode] [List Mode] Instruction Device Step • The following program sets the value for C10 at 10 when X0 goes ON, and at 20 when X1 goes ON. [Ladder Mode] Stores 10 at D0 when X0 goes ON.
  • Page 158: Annunciator Output

    Annunciator output OUT F High Basic Process Redundant Universal LCPU performance Annunciator number (D) Command OUT F (D): Number of the annunciator to be turned ON (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word  (Only F) ...
  • Page 159 Program example • The following program turns F7 ON when X0 goes ON, and stores the value 7 from SD64 to SD79. [Ladder Mode] [List Mode] Instruction Device Step [Operation] X0 ON Adds 1 SD63 SD63 SD64 SD64 SD65 SD65 SD66 SD66 SD67...
  • Page 160: Setting Devices (excluding Annunciators)

     (Other than T, ST, C)    When BL, S, TR, BL\S, or BL\TR is used, refer to the SFC control instructions in the MELSEC-Q/L/QnA Programming Manual (SFC). When F is used, refer to Page 162 Setting annunciators, resetting annunciators. Processing details •...
  • Page 161 Program example • The following program sets Y8B (ON) when X8 goes ON, and resets Y8B (OFF) when X9 goes ON. [Ladder Mode] [List Mode] Instruction Device Step • The following program sets the value of D0 bit 5 (b5) to 1 when X8 goes ON, and set the bit value to 0 when X9 goes ON. [Ladder Mode] [List Mode] Instruction...
  • Page 162: Resetting Devices (excluding Annunciators)

    Word    When BL, S, TR, BL\S, or BL\TR is used, refer to the SFC control instructions in the MELSEC-Q/L/QnA Programming Manual (SFC). When F is used, refer to Page 162 Setting annunciators, resetting annunciators. Processing details • When the execution command is turned ON, the status of the designated devices becomes as shown below:...
  • Page 163 Operation error • There is no operation error in the RST instruction. Program example • The following program sets the value of the data register to 0. [Ladder Mode] Stores the contents at X10 to X1F in D8 when X0 is turned ON. Resets D8 to 0 when X5 is turned ON.
  • Page 164: Setting Annunciators, Resetting Annunciators

    Setting annunciators, resetting annunciators SET F, RST F High Basic Process Redundant Universal LCPU performance Command Command SET (D) : Number of the annunciator to be set (F number) (bits) RST (D) : Number of the annunciator to be reset (F number) (bits) Setting Internal device R, ZR...
  • Page 165 ■RST • The annunciator designated by (D) is turned OFF when the execution command is turned ON. • The annunciator numbers (F numbers) of annunciators that have gone OFF are deleted from the special registers (SD64 to SD79), and the value of SD63 is decremented by 1. •...
  • Page 166: Rising Edge Output, Falling Edge Output

    Rising edge output, falling edge output PLS, PLF High Basic Process Redundant Universal LCPU performance Command Command (D): Pulse conversion device (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word    Processing details ■PLS •...
  • Page 167 ■PLF • Turns ON the designated device when the execution command is turned ON  OFF, and turns OFF the device in any other case the execution command is turned ON  OFF (i.e., at OFF  OFF, OFF  ON or ON  ON of the execution command).
  • Page 168 Program example • The following program executes the PLS instruction when X9 goes ON. [Ladder Mode] [List Mode] Step Instruction Device [Timing Chart] X9 OFF M9 OFF 1 scan • The following program executes the PLF instruction when X9 goes OFF. [Ladder Mode] [List Mode] Instruction...
  • Page 169: Bit Device Output Inversion

    Bit device output inversion High Basic Process LCPU Redundant Universal performance Command (D): Device number of the device to be reversed (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word    Processing details • Reverses the output status of the device designated by (D) when the execution command is turned OFF  ON. Device Device status Prior to FF execution...
  • Page 170 • The following program reverses b10 (bit 10) of D10 when X0 goes ON. [Ladder Mode] [List Mode] Instruction Device Step [Timing Chart] D10 of b10 5 SEQUENCE INSTRUCTIONS 5.3 Output Instructions...
  • Page 171: Pulse Conversion Of Direct Output

    Pulse conversion of direct output DELTA (P) High Basic Process LCPU Redundant Universal performance Command DELTA DELTA Command DELTAP DELTAP (D): Bit for which pulse conversion is to be conducted (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word...
  • Page 172 Program example The DELTA(P) instruction is used for setting preset values of high-speed counter modules. • The following program presets CH1 of the QD62 mounted at slot 0 of the main base unit, when X20 goes ON. [Ladder Mode] Stores the preset value (0) in the buffer memory addresses (0 and 1) of the QD62.
  • Page 173: Shift Instructions

    Shift Instructions Bit device shift SFT(P) High Basic Process Redundant Universal LCPU performance Command Command SFTP SFTP (D): Head number of the devices to be shifted (bits) Setting Internal device R, ZR J\ U\G Constant Others data Word Word  (Other than T, ST, C) ...
  • Page 174 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 175: Master Control Instructions

    Master Control Instructions Setting the master control, resetting the master control MC, MCR High Basic Process Redundant Universal LCPU performance Command Master control ladder Nesting (N0 to N14) (Nesting) (D): Device number to be turned ON (bits) Setting Internal device R, ZR J\...
  • Page 176 ■MC • If the execution command of the MC instruction is ON when master control is started, the result of the operation from the MC instruction to the MCR instruction will be exactly as the instruction (ladder) shows. If the execution command of the MC instruction is OFF, the result of the operation from the MC instruction to the MCR instruction will be as shown below: Device Device status...
  • Page 177 Program example The master control instruction can be used in nesting. The different master control regions are distinguished by nesting (N). Nesting can be performed from N0 to N14. The use of nesting enables the creation of ladders which successively limit the execution condition of the program. A ladder using nesting would appear as shown below: [Ladder as displayed in the GPP ladder mode] [Ladder as it actually operates]...
  • Page 178 Precautions • Nesting can be used up to 15 times (N0 to N14). When using nesting, nests should be inserted from the lower to higher nesting number (N) with the MC instruction, and from the higher to the lower order with the MCR instruction. If this order is reversed, there will be no nesting architecture, and the CPU module will not be capable of performing correct operations.
  • Page 179: Termination Instructions

    Termination Instructions Main routine program end FEND High Basic Process Redundant Universal LCPU performance FEND FEND Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • The FEND instruction is used in cases where the CJ instruction or other instructions are used to create a branch in the sequence program operations, and in cases where the main routine program is to be split from a subroutine program or an interrupt program.
  • Page 180 Program example • The following program uses the CJ instruction. [Ladder Mode] When XB is ON, the program jumps to label P23 and the steps that follow P23 are executed. Executed when XB is OFF. Indicates the termination of the sequence program to be executed when XB is OFF.
  • Page 181: Sequence Program End

    Sequence program end High Basic Process LCPU Redundant Universal performance Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Indicates termination of programs, including main routine program, subroutine program, and interrupt programs. •...
  • Page 182 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 183: Other Instructions

    Other Instructions Sequence program stop STOP High Basic Process Redundant Universal LCPU performance Command STOP STOP Setting Internal device R, ZR J\ U\G Constant Others data Word Word   Processing details • Resets the output (Y) and stops the CPU module operation when the execution command is turned ON. (The same result will take place if switch is turned to the STOP setting.) •...
  • Page 184 Program example • The following program stops the CPU module when X8 goes ON. [Ladder Mode] Stops the programmable controller when X8 goes ON. Sequence program [List Mode] Instruction Device Step 5 SEQUENCE INSTRUCTIONS 5.7 Other Instructions...
  • Page 185: No Operations

    No operations NOP, NOPLF, PAGE n High Basic Process LCPU Redundant Universal performance In the ladder display, NOP is not displayed. Command NOPLF NOPLF PAGE n PAGE n Setting Internal device R, ZR J\ U\G Constant Others data Word Word ...
  • Page 186 Program example ■NOP • Contact closed: Deletes the AND or ANI instruction. [Ladder Mode] [List Mode] Before change Step Instruction Device Changing to NOP After change Instruction Device Step • Contact closed: LD, LDI changed to NOP. (Note carefully that changing the LD and LDI instructions to NOP completely changes the nature of the ladder.) [List Mode] [Ladder Mode]...
  • Page 187 ■NOPLF [Ladder Mode] [List Mode] Step Instruction Device • Printing the ladder will result in the following: NOPLF instruction, inserted as a delimiter NOPLF of ladder blocks, causes print out page to be changed forcibly. • Printing an instruction list with the NOPLF instruction will result in the following: NOPLF Changes print output page after printing NOPLF.
  • Page 188 ■PAGE n [List Mode] [Ladder Mode] Step Instruction Device 5 SEQUENCE INSTRUCTIONS 5.7 Other Instructions...
  • Page 189: Basic Instructions

    BASIC INSTRUCTIONS Comparison Operation Instructions BIN 16-bit data comparisons LD, AND, OR High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of Command Command Command (S1), (S2): Data for comparison or head number of the devices where the data for comparison is stored (BIN 16 bits) Setting Internal device R, ZR...
  • Page 190 Program example • The following program compares the data at X0 to XF with the data at D3, and turns Y33 ON if the data is identical. [Ladder Mode] [List Mode] Instruction Device Step • The following program compares BIN value K100 to the data at D3, and establishes continuity if the data in D3 is something other than 100.
  • Page 191: Bin 32-bit Data Comparisons

    BIN 32-bit data comparisons LDD, ANDD, ORD High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of Command Command Command (S1), (S2): Data for comparison or head number of the devices where the data for comparison is stored (BIN 32 bits) Setting Internal device R, ZR...
  • Page 192 Program example • The following program compares the data at X0 to X1F with the data at D3 and D4, and turns Y33 ON, if the data at X0 to X1F and the data at D3 and D4 match. [Ladder Mode] [List Mode] Device Step...
  • Page 193: Floating-point Data Comparisons (single Precision)

    Floating-point data comparisons (single precision) LDE, ANDE, ORE Ver. High Basic Process Redundant Universal LCPU performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of Command Command Command (S1), (S2): Data for comparison or head number of the devices where the data for comparison is stored (real number) Setting Internal device R, ZR...
  • Page 194 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 195: Floating-point Data Comparisons (double Precision)

    Floating-point data comparisons (double precision) LDED, ANDED, ORED High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ED Command Command Command (S1), (S2): Data for comparison or head number of the devices where the data for comparison is stored (real number) Setting Internal device R, ZR...
  • Page 196 Program example • The following program compares 64-bit floating decimal point real number data at D0 to D3 with 64-bit floating decimal point real number data at D4 to D7. [Ladder Mode] [List Mode] Instruction Device Step • The following program compares the floating decimal point real number 1.23 with the 64-bit floating decimal point real number data at D4 to D7.
  • Page 197 Precautions • Since the number of digits of the real number that can be input by Programing Tool is up to 15 digits, the comparison with the real number whose number of significant digits is 16 or more cannot be made by the instruction shown in this section. When judging match/mismatch with the real number whose significant digits is 16 or more by the instruction in this section, compare it with the approximate values of the real number to be compared and judge by the sizes.
  • Page 198: Character String Data Comparisons

    Character string data comparisons LD$, AND$, OR$ Basic High Process Redundant Universal LCPU performance indicates an instruction symbol of Command Command Command (S1), (S2): Data for comparison or head number of the devices where the data for comparison is stored (character string) Setting Internal device R, ZR...
  • Page 199 • If the character strings are different, the first different sized character code will determine whether the character string is larger or smaller. (S1) (S2) (S1)+1 (S2)+1 (S1)+2 (S2)+2 "12345" "12435" Instruction symbol Comparison operation result Instruction symbol Comparison operation result Non-continuity $<= Continuity...
  • Page 200 Program example • The following program compares character strings stored following D0 and characters following D10. [Ladder Mode] [List Mode] Device Step Instruction • The following program compares the character string "ABCDEF" with the character string stored following D10. [Ladder Mode] [List Mode] Device Step...
  • Page 201: Bin 16-bit Block Data Comparisons

    BIN 16-bit block data comparisons BKCMP(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of Command BKCMP BKCMP Command BKCMP BKCMP (S1): Data to be compared or head number of the devices where the data to be compared is stored (BIN 16 bits) (S2): Head number of the devices where the comparison data is stored (BIN 16 bits) (D): Head number of the devices where the comparison operation result will be stored (bits) Number of comparison data blocks (BIN 16 bits)
  • Page 202 • The results of the comparison operations for the individual instructions are as follows: Instruction symbol Condition Comparison Instruction symbol Condition Comparison operation result operation result BKCMP= (S1)=(S2) ON (1) BKCMP= (S1)(S2) OFF (0) BKCMP<> (S1)(S2) BKCMP<> (S1)=(S2) BKCMP> (S1)>(S2) BKCMP>...
  • Page 203 • The following program compares, when X1C is turned ON, the constant K1000 with the data stored at D10 to D13, and stores the operation result at b4 to b7 in D0. [Ladder Mode] [List Mode] Device Step Instruction [Operation] 2000 (BIN) 1000 (BIN) 1000...
  • Page 204: Bin 32-bit Block Data Comparisons

    BIN 32-bit block data comparisons DBKCMP(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported indicates an instruction symbol of Command DBKCMP DBKCMP Command DBKCMP...
  • Page 205 • The results of the comparison operations for the individual instructions are as follows: Instruction symbol Condition Comparison Instruction symbol Condition Comparison operation result operation result DBKCMP= (S1)=(S2) ON (1) DBKCMP= (S1)(S2) OFF (0) DBKCMP<> (S1)(S2) DBKCMP<> (S1)=(S2) DBKCMP> (S1)>(S2) DBKCMP>...
  • Page 206 • The following program compares the constant with the value data stored at D0 to D9, and then stores the operation result into D10.5 to D10.9, when M0 is turned on. [Ladder Mode] [List Mode] Instruction Device Step [Operation] -70000 D1,D0 D10.5 50000...
  • Page 207: Bin 16-bit Data Comparisons (small, Match, Large)

    BIN 16-bit data comparisons (small, match, large) CMP(P) Ver. Ver. High Basic Process Redundant LCPU Universal performance • LCPU: The serial number (first five digits) is "16042" or later. • QnUDVCPU: The serial number (first five digits) is "16043" or later. Command Command CMPP...
  • Page 208 Program example • Program that compares the value of D0 with the constant value K100 Compare K100 with D0. M0 turns on when K100 > D0. M1 turns on when K100 = D0. M2 turns on when K100 < D0. 6 BASIC INSTRUCTIONS 6.1 Comparison Operation Instructions...
  • Page 209: Bin 32-bit Data Comparisons (small, Match, Large)

    BIN 32-bit data comparisons (small, match, large) DCMP(P) Ver. Ver. High Basic Process Redundant LCPU Universal performance • LCPU: The serial number (first five digits) is "16042" or later. • QnUDVCPU: The serial number (first five digits) is "16043" or later. Command DCMP DCMP...
  • Page 210: Bin 16-bit Data Band Comparisons

    BIN 16-bit data band comparisons ZCP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • LCPU: The serial number (first five digits) is "16042" or later. • QnUDVCPU: The serial number (first five digits) is "16043" or later. Command Command ZCPP ZCPP...
  • Page 211 Program example • Program that compares the band of the value of D0 with the lower limit value (K100) and the upper limit value (K120) Compare D0 with lower limit value (K100) and upper limit value (K120). M0 turns on when K100 > D0. M1 turns on when K100 ≤...
  • Page 212: Bin 32-bit Data Band Comparisons

    BIN 32-bit data band comparisons DZCP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • LCPU: The serial number (first five digits) is "16042" or later. • QnUDVCPU: The serial number (first five digits) is "16043" or later. Command DZCP DZCP Command...
  • Page 213 Program example • Program that compares the bands of the values of D0 and D1 with the lower limit value (K100) and upper limit value (K120) Compare D0 and D1 with lower limit value (K100) and upper limit value (K120). M0 turns on when K100 >...
  • Page 214: Floating Point Comparisons (single Precision)

    Floating point comparisons (single precision) ECMP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command ECMP ECMP Command ECMPP ECMPP (S1): Comparison data or start number of the devices where the comparison data is stored (real number) (S2): Comparison data or start number of the devices where the comparison data is stored (real number) (D): Start bit device number to which the comparison result is output (Bit) Setting...
  • Page 215 Program example • Program that compares the values of D0 and D1 with the real number 1.23 [Ladder Mode] Compare E1.23 with D0 and D1. M0 turns on when E1.23 > D0 and D1. M1 turns on when E1.23 = D0 and D1. M2 turns on when E1.23 <...
  • Page 216: Floating Point Comparisons (double Precision)

    Floating point comparisons (double precision) EDCMP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command EDCMP EDCMP Command EDCMPP EDCMPP (S1): Comparison data or start number of the devices where the comparison data is stored (real number) (S2): Comparison data or start number of the devices where the comparison data is stored (real number) (D): Start bit device number to which the comparison result is output (Bit) Setting...
  • Page 217 Program example • Program that compares the values of D0 to D3 with the real number 1.23 [Ladder Mode] Compare E1.23 with D0 to D3. M0 turns on when E1.23 > D0 to D3. M1 turns on when E1.23 = D0 to D3. M2 turns on when E1.23 <...
  • Page 218: Floating Point Band Comparisons (single Precision)

    Floating point band comparisons (single precision) EZCP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command EZCP EZCP Command EZCPP EZCPP (S1): Start number of the devices where the lower limit value is stored (real number) (S2): Start number of the devices where the upper limit value is stored (real number) (S3): Data to be compared or start number of the device where the data to be compared is stored (real number) (D): Start bit device number to which the comparison result is output (Bit)
  • Page 219 Program example • Program that compares the values of D0 and D1 with the lower limit value (E-1.23) and upper limit value (E1.23) [Ladder Mode] Compare D0 and D1 with lower limit value (E-1.23) and upper limit value (E1.23). M0 turns on when E-1.23 > D0 and D1. M1 turns on when E-1.23 ≤...
  • Page 220: Floating Point Band Comparisons (double Precision)

    Floating point band comparisons (double precision) EDZCP(P) Ver. Ver. High Basic Process Redundant Universal LCPU performance • QnUDVCPU, LCPU: The serial number (first five digits) is "16112" or later. Command EDZCP EDZCP Command EDZCPP EDZCPP (S1): Start number of the devices where the lower limit value is stored (real number) (S2): Start number of the devices where the upper limit value is stored (real number) (S3): Data to be compared or start number of the device where the data to be compared is stored (real number) (D): Start bit device number to which the comparison result is output (Bit)
  • Page 221 Program example • Program that compares the values of D0 to D3 with the lower limit value (E-1.23) and upper limit value (E1.23). [Ladder Mode] Compare D0 to D3 with lower limit value (E-1.23) and upper limit value (E1.23). M0 turns on when E-1.23 > D0 to D3. M1 turns on when E-1.23 ≤...
  • Page 222: Arithmetic Operation Instruction

    Arithmetic Operation Instructions BIN 16-bit addition and subtraction operations +(P), -(P) [When two data are set] High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of Command Command +P, P (S): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 16 bits) (D): Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits) Setting Internal device...
  • Page 223 ■- • Subtracts 16-bit BIN data designated by (D) from 16-bit BIN data designated by (S) and stores the result of the subtraction at the device designated by (D). 5678 (BIN) 1234 (BIN) 4444 (BIN) • Values for (S) and (D) can be designated between -32768 and 32767 (BIN, 16 bits). •...
  • Page 224 +(P), -(P) [When three data are set] indicates an instruction symbol of Command Command +P, P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 16 bits) (D): Head number of the devices where the operation result will be stored (BIN 16 bits) Setting...
  • Page 225 Operation error • There is no operation error in the +(P) or -(P) instruction. Program example • The following program adds, when X5 is turned ON, the data at D3 and D0 and outputs the operation result at Y38 to Y3F. [Ladder Mode] [List Mode] Device...
  • Page 226: Bin 32-bit Addition And Subtraction Operations

    BIN 32-bit addition and subtraction operations D+(P), D-(P) [When two data are set] High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command D+, D Command D+P, D P (S): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 32 bits) (D): Head number of the devices where the data to be added to/subtracted from is stored (BIN 32 bits) Setting Internal device...
  • Page 227 ■D- • Subtracts 32-bit BIN data designated by (D) from 32-bit BIN data designated by (S) and stores the result of the subtraction at the device designated by (D). D +1 b16 b15 b16 b15 b16 b15 567890 (BIN) 123456 (BIN) 444434 (BIN) •...
  • Page 228 D+(P), D-(P) [When three data are set] indicates an instruction symbol of D+/ D Command D+, D Command D+P, D P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BIN 32 bits) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 32 bits) (D): Head number of the devices where the multiplication/division operation result will be stored (BIN 32 bits) Setting...
  • Page 229 ■D- • Subtracts 32-bit BIN data designated by (S1) from 32-bit BIN data designated by (S2) and stores the result of the subtraction at the device designated by (D). b16 b15 b16 b15 b16 b15 567890 (BIN) 123456 (BIN) 444434 (BIN) •...
  • Page 230: Bin 16-bit Multiplication And Division Operations

    BIN 16-bit multiplication and division operations *(P), /(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of * Command *, / Command *P, / P (S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BIN 16 bits) (S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BIN 16 bits) (D): Head number of the devices where the multiplication/division operation result will be stored (BIN 32 bits) Setting...
  • Page 231 ■/ • Divides BIN 16-bit data designated by (S1) and BIN 16-bit data designated by (S2), and stores the result in the device designated by (D). Quotient Remainder 5678 (BIN) 1234 (BIN) 4 (BIN) 742 (BIN) • If a word device has been used, the result of the division operation is stored as 32 bits, and both the quotient and remainder are stored;...
  • Page 232: Bin 32-bit Multiplication And Division Operations

    BIN 32-bit multiplication and division operations D*(P), D/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of Command D*, D/ Command D*P, D/P (S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BIN 32 bits) (S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BIN 32 bits) (D): Head number of the devices where the multiplication/division operation result will be stored (BIN 64 bits) Setting...
  • Page 233 ■D/ • Divides BIN 32-bit data designated by (S1) and BIN 32-bit data designated by (S2), and stores the result in the device designated by (D). b31 b16 b31 b16 b31 b16 567890 (BIN) 123456 (BIN) 4 (BIN) 74066 (BIN) •...
  • Page 234: Bcd 4-digit Addition And Subtraction Operations

    BCD 4-digit addition and subtraction operations B+(P), B-(P) [When two data are set] High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of B+/B Command B+, B Command B+P, B P (S): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 4 digits) (D): Head number of the devices where the data to be added to/subtracted from is stored (BCD 4 digits) Setting Internal device...
  • Page 235 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 236 B+(P), B-(P) [When three data are set] indicates an instruction symbol of B+/B- Command B+, B- Command B+P, B-P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BCD 4 digits) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 4 digits) (D): Head number of the devices where the operation result will be stored (BCD 4 digits) Setting...
  • Page 237 Program example • The following program adds the D3 BCD data and the Z1 BCD data when X20 goes ON, and outputs the result to Y8 to Y17. [Ladder Mode] [List Mode] Step Instruction Device • The following program subtracts the BCD data at D20 from the BCD data at D10 when X20 goes ON, and stores the result at R10.
  • Page 238: Bcd 8-digit Addition And Subtraction Operations

    BCD 8-digit addition and subtraction operations DB+(P), DB-(P) [When two data are set] High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DB+/DB- Command DB+, DB- Command DB+P, DB-P (S): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 8 digits) (D): Head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits) Setting Internal device...
  • Page 239 Operation error • In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/       4100 The (S) or (D) BCD data is outside the 0 to 99999999 range.
  • Page 240 DB+(P), DB-(P) [When three data are set] indicates an instruction symbol of DB+/ DB Command DB+, DB- Command DB+P, DB-P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 8 digits) (D): Head number of the devices where the addition/subtraction operation result is stored (BCD 8 digits) Setting...
  • Page 241 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 242: Bcd 4-digit Multiplication And Division Operations

    BCD 4-digit multiplication and division operations B*(P), B/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of B ,B/ Command , B/ Command P, B/P (S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BCD 4 digits) (S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BCD 4 digits) (D): Head number of the devices where the multiplication/division operation result will be stored (BCD 8 digits) Setting...
  • Page 243 Program example • The following program multiplies, when X20 is turned ON, the BCD data at X0 to XF by the BCD data at D8 and stores the operation result at D0 to D1. [Ladder Mode] [List Mode] Instruction Device Step [Operation] D1 (Upper 4 digits)
  • Page 244: Bcd 8-digit Multiplication And Division Operations

    BCD 8-digit multiplication and division operations DB*(P), DB/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of DB* , DB/. Command DB , DB/ Command DB P, DB/P (S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BCD 8 digits) (S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BCD 8 digits) (D): Head number of the devices where the multiplication/division operation result will be stored (BCD 16 digits) Setting...
  • Page 245 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 246: Addition And Subtraction Of Floating-point Data (single Precision)

    Addition and subtraction of floating-point data (single precision) E+(P), E-(P) [When two data are set] Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of E+/E- Command E+, E-...
  • Page 247 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 248 E+(P), E-(P) [When three data are set] indicates an instruction symbol of E+/E-. Command E+, E- Command E+P, E-P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (real number) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting...
  • Page 249 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 250: Addition And Subtraction Of Floating-point Data (double Precision)

    Addition and subtraction of floating-point data (double precision) ED+(P), ED-(P) [When two data are set] High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ED+/ED-. Command ED+, ED- Command ED+P, ED-P (S): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number) (D): Head number of the devices where the data to be added to/subtracted from is stored (real number) Setting Internal device...
  • Page 251 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 252 ED+(P), ED-(P) [When three data are set] indicates an instruction symbol of ED+/ED-. Command ED+, ED- Command ED+P, ED-P (S1): Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (real number) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting...
  • Page 253 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 254: Multiplication And Division Of Floating-point Data (single Precision)

    Multiplication and division of floating-point data (single precision) E*(P), E/(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of E* , E/ Command E* , E/ Command...
  • Page 255 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 256: Multiplication And Division Of Floating-point Data (double Precision)

    Multiplication and division of floating-point data (double precision) ED*(P), ED/(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of ED*, ED/. Command ED*, ED/ Command ED* P, ED/P (S1): Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (real number) (S2): Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (real number) (D): Head number of the devices where the operation result will be stored (real number) Setting...
  • Page 257 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 258: Bin 16-bit Data Block Addition And Subtraction Operations

    BIN 16-bit data block addition and subtraction operations BK+(P), BK-(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BK+, BK- . Command BK+, BK- Command BK+P, BK-P (S1): Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits) (S2): Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 16 bits) (D): Head number of the devices where the operation result will be stored (BIN 16 bits) Number of addition/subtraction data blocks (BIN 16 bits)
  • Page 259 ■BK- • Subtracts n points of BIN data from the device designated by (S1) and n-points of BIN data from the device designated by (S2) and stores the result to the area starting from the device designated by (D). 8765 (BIN) 1234 (BIN)
  • Page 260 Program example • The following program adds, when X20 is turned ON, the data stored at D100 to D103 to the data stored at R0 to R3 and stores the operation result into the area starting from D200. [Ladder Mode] [List Mode] Step Instruction...
  • Page 261: Bin 32-bit Data Block Addition And Subtraction Operations

    BIN 32-bit data block addition and subtraction operations DBK+(P), DBK-(P) Ver. High Basic Process Redundant Universal LCPU performance • QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later • Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported indicates an instruction symbol of DBK+, DBK- . Command DBK+, DBK- (S1)
  • Page 262 • The following will happen if an overflow occurs in an operation result: The carry flag (SM700) in this case does not go ON. K2147483647 K 2147483647 ) ( 80000001 (00000002 (7FFFFFFF K2147483647 K 2147483647 ( FFFFFFFE ) ( 7FFFFFFF (80000001 ■DBK- •...
  • Page 263 Program example • The following program adds the value data stored at R0 to R5 to the constant, and then stores the operation result into D30 to D35, when M0 is turned on. [Ladder Mode] [List Mode] Device Step Instruction [Operation] 600000 723456...
  • Page 264: Linking Character Strings

    Linking character strings $+(P) [When two data are set] Basic High Process Redundant Universal LCPU performance Command Command (S): Data for linking or head number of the devices where the data for linking is stored (character string) (D): Head number of the devices where the data to be linked is stored (character string) Setting Internal device R, ZR...
  • Page 265 Program example • The following program links the character string stored from D10 to D12 to the character string "ABCD" when X0 is ON. [Ladder Mode] [List Mode] Device Step Instruction [Operation] "ABCD" Automatically stores "00 ". 6 BASIC INSTRUCTIONS 6.2 Arithmetic Operation Instructions...
  • Page 266 $+(P) [When three data are set] Command Command (S1): Data for linking or head number of the devices where the data for linking is stored (character string) (S2): Data to be linked or head number of the devices where the data to be linked is stored (character string) (D): Head number of the devices where the linking result will be stored (character string) Setting Internal device...
  • Page 267: 16-bit Bin Data Increment, 16-bit Bin Data Decrement

    16-bit BIN data increment, 16-bit BIN data decrement INC(P), DEC(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of INC/DEC. Command INC, DEC Command INCP, DECP (D): Head number of devices for INC (+1)/DEC (-1) operation (BIN 16 bits) Setting Internal device R, ZR...
  • Page 268 Program example • The following program outputs the present value at the counter C0 to C20 to the area Y30 to Y3F in BCD, every time X8 is turned ON. (When present value is less than 9999) [Ladder Mode] Outputs the present value of (0+Z1) to Y30 to Y3F in BCD.
  • Page 269: 32-bit Bin Data Increment, 32-bit Bin Data Decrement

    32-bit BIN data increment, 32-bit BIN data decrement DINC(P), DDEC(P) High Basic Process LCPU Redundant Universal performance indicates an instruction symbol of DINC/DDEC. Command DINC, DDEC Command DINCP, DDECP (D): Head number of devices for DINC(+1) or DDEC(-1) operation (BIN 32 bits) Setting Internal device R, ZR...
  • Page 270 Program example • The following program adds 1 to the data at D0 and D1 when X0 is ON. [Ladder Mode] [List Mode] Instruction Device Step • The following program adds 1 to the data set at X10 to X27 when X0 goes ON, and stores the result at D3 and D4. [Ladder Mode] [List Mode] Device...
  • Page 271: Data Conversion Instructions

    Data Conversion Instructions Conversion from BIN data to BCD 4-digit data, conversion from BIN data to BCD 8-digit data BCD(P), DBCD(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BCD/DBCD. Command BCD, DBCD Command BCDP, DBCDP (S): BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits) (D): Head number of the devices where BCD data will be stored (BCD 4/8 digits) Setting...
  • Page 272 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 273: Conversion From Bcd 4-digit Data To Bin Data, Conversion From Bcd 8-digit Data To Bin Data

    Conversion from BCD 4-digit data to BIN data, conversion from BCD 8-digit data to BIN data BIN(P), DBIN(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of BIN/DBIN. Command BIN, DBIN Command BINP, DBINP (S): BCD data or head number of the devices where the BCD data is stored (BCD 4/8 digits) (D): Head number of the devices where BIN data will be stored (BIN 16/32 bits) Setting Internal device...
  • Page 274 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 275: Conversion From Bin 16-bit Data To Floating-point Data (single Precision), Conversion From Bin 32-bit Data To Floating-point Data (single Precision)

    Conversion from BIN 16-bit data to floating-point data (single precision), conversion from BIN 32-bit data to floating-point data (single precision) FLT(P), DFLT(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of FLT/DFLT.
  • Page 276 • Due to the fact that 32-bit floating decimal point type real numbers are processed by simple 32-bit processing, the number of significant digits is 24 bits if the display is binary and approximately 7 digits if the display is decimal. For this reason, if the integer exceeds the range of -16777216 to 16777215 (24-bit BIN value), errors can be generated in the conversion value.
  • Page 277: Conversion From Bin 16-bit Data To Floating-point Data (double Precision), Conversion From Bin 32-bit Data To Floating-point Data (double Precision)

    Conversion from BIN 16-bit data to floating-point data (double precision), conversion from BIN 32-bit data to floating-point data (double precision) FLTD(P), DFLTD(P) High Basic Process Redundant LCPU Universal performance indicates an instruction symbol of FLTD/DFLTD. Command FLTD, DFLTD Command FLTDP, DFLTDP (S): Integer data to be converted to 64-bit floating decimal point data or head number of the devices where the integer data is stored (BIN 16/32 bits) (D): Head number of the devices where the converted 64-bit floating decimal point data will be stored (real number) Setting...
  • Page 278 Program example • The following program converts the BIN 16-bit data at D20 to a 64-bit floating decimal point type real number and stores the result at D0 to D3. [Ladder Mode] [List Mode] Instruction Device Step [Operation] Conversion to real number 15923 15923 BIN value...
  • Page 279: Conversion From Floating-point Data To Bin 16-bit Data (single Precision), Conversion From Floating-point Data To Bin 32-bit Data (single Precision)

    Conversion from floating-point data to BIN 16-bit data (single precision), conversion from floating-point data to BIN 32-bit data (single precision) INT(P), DINT(P) Ver. High Basic Process LCPU Redundant Universal performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. indicates an instruction symbol of INT/DINT.
  • Page 280 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/Q01 4140 The specified device value is not within the following range: ...
  • Page 281: Conversion From Floating-point Data To Bin 16-bit Data (double Precision), Conversion From Floating-point Data To Bin 32-bit Data (double Precision)

    Conversion from floating-point data to BIN 16-bit data (double precision), conversion from floating-point data to BIN 32-bit data (double precision) INTD(P), DINTD(P) High Basic Process Redundant LCPU Universal performance indicates an instruction symbol of INTD/DINTD. Command INTD, DINTD Command INTDP, DINTDP (S): 64-bit floating decimal point data to be converted to BIN value or head number of the devices where the floating decimal point data is stored (real number) (D): Head number of the devices where the converted BIN value will be stored (BIN 16/32 bits) Setting...
  • Page 282 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/Q01 (S) is -0, a subnormal number, NaN (not a number), , or a 4140 ...
  • Page 283: Conversion From Bin 16-bit To Bin 32-bit Data

    Conversion from BIN 16-bit to BIN 32-bit data DBL(P) High Basic Process LCPU Redundant Universal performance Command Command DBLP DBLP (S): BIN 16-bit data or head number of the devices where the BIN 16-bit data is stored (BIN 16 bits) (D): Head number of the devices where the converted BIN 32-bit data will be stored (BIN 32 bits) Setting Internal device...
  • Page 284: Conversion From Bin 32-bit To Bin 16-bit Data

    Conversion from BIN 32-bit to BIN 16-bit data WORD(P) High Basic Process Redundant Universal LCPU performance Command WORD WORD Command WORDP WORDP (S): BIN 32-bit data or head number of the devices where the BIN 32-bit data is stored (BIN 32 bits) (D): Head number of the devices where the converted BIN 16-bit data will be stored (BIN 16 bits) Setting Internal device...
  • Page 285: Conversion From Bin 16-bit Data To Gray Code, Conversion From Bin 32-bit Data To Gray Code

    Conversion from BIN 16-bit data to Gray code, conversion from BIN 32-bit data to Gray code GRY(P), DGRY(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of GRY, DGRY. Command GRY, DGRY Command GRYP, DGRYP (S): BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits) (D): Head number of the devices where the converted Gray code will be stored (BIN 16/32 bits) Setting Internal device...
  • Page 286 Program example • The following program converts the BIN data at D100 to Gray code when X10 is ON, and stores result at D200. [Ladder Mode] [List Mode] Device Step Instruction • The following program converts the BIN data at D10 and D11 to Gray code when X1C is ON, and stores it at D100 and D101.
  • Page 287: Conversion From Gray Code To Bin 16-bit Data, Conversion From Gray Code To Bin 32-bit Data

    Conversion from Gray code to BIN 16-bit data, conversion from Gray code to BIN 32-bit data GBIN(P), DGBIN(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of GBIN/DGBIN. Command GBIN, DGBIN Command GBINP, DGBINP (S): Gray code data or head number of the devices where the Gray code data is stored (BIN 16/32 bits) (D): Head number of the devices where the converted BIN data will be stored (BIN 16/32 bits) Setting Internal device...
  • Page 288 Operation error • In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. Error Error details Q00J/ QnPH QnPRH LCPU code Q00/     ...
  • Page 289: Complement Of 2 Of Bin 16-bit Data (sign Inversion), Complement Of 2 Of Bin 32-bit Data (sign Inversion)

    Complement of 2 of BIN 16-bit data (sign inversion), complement of 2 of BIN 32-bit data (sign inversion) NEG(P), DNEG(P) High Basic Process Redundant Universal LCPU performance indicates an instruction symbol of NEG/DNEG. Command NEG, DNEG Command NEGP, DNEGP (D): Head number of the devices where the data for which complement of 2 is performed is stored (BIN 16/32 bits) Setting Internal device R, ZR...
  • Page 290 Program example • The following program calculates a total for the data at D10 through D20 when XA goes ON, and seeks an absolute value if the result is negative. [Ladder Mode] M3 is turned ON if D10 < D20. Executes "D10 - D20".
  • Page 291: Floating-point Sign Inversion (single Precision)

    Floating-point sign inversion (single precision) ENEG(P) Ver. High Basic Process Redundant Universal LCPU performance • Basic model QCPU: The serial number (first five digits) is "04122" or later. Command ENEG ENEG Command ENEGP ENEGP (D): Head number of the devices where the 32-bit floating decimal point data whose sign is to be reversed is stored (real number) Setting Internal device R, ZR...
  • Page 292: Floating-point Sign Inversion (double Precision)