N-Bit Shift To Right Of N-Bit Data, N-Bit Shift To Left Of N-Bit Data - Mitsubishi Electric MELSEC-Q/L Programming Manual

n-bit shift to right of n-bit data, n-bit shift to left of n-bit data

SFTBR(P), SFTBL(P)
High
Basic
Process
performance
• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five digits) is "10102" or later
• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported
SFTBR, SFTBL
SFTBRP, SFTBLP
(D): Head number of the devices to be shifted (bits)
n1: Number of bits to be shifted (BIN 16 bits)
n2: Number of shifts (BIN 16 bits)
Setting Internal device
data
Bit
*1

(D)

n1

n2
*1 T, ST, and C devices are not available.
Processing details
■SFTBR(P)
• This instruction shifts the n1 bits data in the devices starting from the device specified by (D) to the right by n2 bits.
n1=10, n2=4
D +9 D +8 D +7
D +9 D +8 D +7
0 0 0
Filled with 0s
• n1 and n2 are specified under the condition that n1 is larger than n2. If the value of n2 is equal to or larger than the value of
n1, the remainder of n2 / n1 (n2 divided by n1) is used for a shift. However, if the remainder of n2 / n1 is 0, the instruction
will be not processed.
• This instruction specifies n1 ranged from 1 to 64.
• Bits starting from the highest bit to n2th bit are filled with 0s. If the value of n2 is larger than the value of n1, the remainder
of n2 / n1 will be 0.
• If the value specified by n1 or n2 is 0, the instruction will be not processed.
7 APPLICATION INSTRUCTIONS
396
7.3 Shift Instructions
Ver.
Redundant
Universal LCPU
R, ZR
Word
 
 
 
n1
D +6 D +5 D +4 D +3
0 1 1 1
D +6 D +5 D +4 D +3
0 1 1 1
indicates an instruction symbol of SFTBR/SFTBL.
Command
Command
J\
Bit Word



n2
D +2 D +1 D
1 0 0
D D +1 D
+2
0 1 1
n1
D
P D n1
U\G Zn Constant
K, H
Carry flag
(SM700)
n2
n2
Others


