Mitsubishi Electric MELSEC-Q/L Programming Manual page 866

Managing the multiple CPU high speed transmission area
The multiple CPU high speed transmission area is managed by blocks in units of 16 words.
The following table shows the number of blocks that can be used in each CPU and the number of blocks used in the
instruction.
Number of CPU modules
2
3
4
*1 For setting of the system area, refer to the QCPU User's Manual (Multiple CPU System).
The following shows configuration of the multiple CPU high speed transmission area when the multiple CPU system is
configured with three CPU modules and the system area size is 1K word.
Multiple CPU high speed
transmission area in
CPU No.1
Send area
22
(to CPU No.2)
blocks
Send area
22
(to CPU No.3)
blocks
Receive area
22
(from CPU
blocks
No.2)
22
blocks
Receive area
22
(from CPU
blocks
No.3)
22
blocks
Number of blocks used for the instruction
The number of blocks used for the instruction depends on the number of write points.
The following table shows the number of blocks used for the instruction.
Number of write/read points specified by
the instruction
1 to 4
5 to 20
21 to 36
37 to 52
53 to 68
69 to 84
85 to 100
10 MULTIPLE CPU HIGH-SPEED TRANSMISSION DEDICATED INSTRUCTIONS
864
10.1 Overview
System area
1K points
46
22
14
Multiple CPU high speed Multiple CPU high speed
transmission area in transmission area in
CPU No.2 CPU No.3
Receive area
22
(from CPU
blocks
No.1)
Receive area
(from CPU
No.1)
Send area
22
(to CPU No.1)
blocks
Send area Receive area
(to CPU No.3) (from CPU
No.2)
Send area
(to CPU No.1)
Receive area Send area
(from CPU (to CPU No.2)
No.3)
D(P).DDWR instruction
1
2
3
4
5
6
7
*1
22
blocks
22
blocks
22
blocks
22
blocks
2K points
110
54
35
D(P).DDRD instruction
1