Chapter 10 Multiple Cpu High-Speed Transmission Dedicated Instructions; Overview - Mitsubishi Electric MELSEC-Q/L Programming Manual

10
MULTIPLE CPU HIGH-SPEED TRANSMISSION
DEDICATED INSTRUCTIONS
10.1

Overview

The multiple CPU high-speed transmission dedicated instruction directs the Universal model QCPU to write/read device data
to/from the Universal model QCPU in another CPU.
The following shows an operation when CPU No.1 writes device data to CPU No.2 with the multiple CPU high-speed
transmission dedicated instruction.
CPU No.1
User program
DP.DDWR U3E1 D0 D100 D200 M0
D0
D100
The multiple CPU high-speed transmission dedicated instruction in either host CPU or another CPU (target
CPU module of instruction) is available only for the following CPU modules.
• Q03UDCPU, Q04UDHCPU, Q06UDHCPU: The serial number (first five digits) is "10012" or later.
• Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, Q26UDHCPU
• Built-in Ethernet port QCPU
Parameter setting and system configuration to execute the instruction
The multiple CPU high-speed transmission dedicated instruction can be executed in the following parameter setting and
system configuration.
• For CPU No. 1, QnUD(H)CPU or, Built-in Ethernet port QCPU is used.
• The multiple CPU high speed main base unit (Q3DB) is used.
• "Use multiple CPU high speed transmission" is selected in the Multiple CPU settings screen of PLC parameter.
CPU No.2
D0
Writing
D200
10 MULTIPLE CPU HIGH-SPEED TRANSMISSION DEDICATED INSTRUCTIONS
10
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10.1 Overview