Arc Sine Operation On Floating-Point Data (Single Precision) - Mitsubishi Electric MELSEC-Q/L Programming Manual

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Arc sine operation on floating-point data (single precision)

ASIN(P)
Basic
High
Process
performance
(S): SIN value of which the SIN
(D): Head number of the devices where the operation result will be stored (real number)
Setting
Internal device
data
Bit
(S)
(D)
*1 Applicable for the Universal model QCPU, LCPU.
Processing details
-1
• Returns the SIN
S
+1
-1
SIN (
32-bit floating-point
real number
• The SIN value designated by (S) can be in the range from -1.0 to 1.0.
• The angle (operation result) stored at (D) is stored in radian units. For more information on the conversion between radian
and angle data, see description of RAD and DEG instructions.
• When an input value is set using a programming tool, a rounding error may occur. For precautions, refer to Page 89
Precautions.
Operation error
• In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Error
Error details
code
4100
The value specified by (S) is not within the range between -1.0 and 1.0.
The specified device value is -0.
4140
The specified device value is not within the following range:
-126
 | Specified device value | <2
0, 2
The specified device value is -0, unnormalized number, nonnumeric, and .
4141
The operation result exceeds the following range.
(when an overflow occurs)
|Operation result| < 2
*2 There are CPU modules that will not result in an operation error if -0 is specified. For details, refer to Page 87 Using single/double-
precision real number data.
7 APPLICATION INSTRUCTIONS
606
7.12 Special Function Instructions
Redundant Universal
LCPU
ASIN
ASINP
-1
(inverse sine) value is obtained or head number of the devices where the SIN value is stored (real number)
R, ZR
Word
angle of the SIN value designated by (S), and stores operation results at word device designated by (D).
S
D
+1
)
32-bit floating-point
real number
*2
128
128
Command
Command
J\
Bit
Word
D
Q00J/
Q00/
Q01
S
D
ASIN
S
D
ASINP
U\G
Zn
Constant
E
*1
*1
QnH
QnPH
QnPRH
Others
QnU
LCPU

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