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Program example
■Program example when SM796 to SM799 are used as an interlock
The following shows a program that executes the D.DDWR instruction to CPU No.2 at the rise of X0, and executes the
D.DDWR instruction to CPU No.3 at the rise of X1.
The maximum number of used blocks for multiple CPU high-speed transmission dedicated instruction
SM402
0
Turn-on for one
scan after RUN
SM402
8
Turn-on for one
scan after RUN
The DDWR instruction is executed to CPU No.2 at the rise of X0
X0
11
Execution command of the
DDWR instruction to CPU No.2
M0
SM797
14
During execution
Number of used
of the DDWR
blocks information
instruction to
(CPU No.2)
CPU No.3
The DDWR instruction is executed to CPU No.3 at the rise of X1
X1
29
During execution of the DDWR
instruction to CPU No.3
M3
SM798
32
During execution
Number of used
of the DDWR
blocks information
instruction to
(CPU No.3)
CPU No.3
D.DDWRH3E1
D0
Completion
status
(CPU No.2)
D.DDWRH3E2
D2
Completion
status
(CPU No.3)
10 MULTIPLE CPU HIGH-SPEED TRANSMISSION DEDICATED INSTRUCTIONS
MOV
K7
SD797
Maximum number of
used blocks
(CPU No.2)
MOV
K7
SD798
Maximum number of
used blocks
(CPU No.3)
MOV
K100
D1
Number of write points
to CPU No.2
MOV
K100
D3
Number of write points
to CPU No.3
SET
M0
During execution the
DDWR instruction to
CPU No.3
ZR0
ZR0
M1
Write data
Write data
Completion
to CPU No.2
to CPU No.2
device
(CPU No.2)
RST
M0
During execution of the
DDWR instruction to CPU No.2
SET
M3
During execution the
DDWR instruction to
CPU No.3
ZR1000
ZR1000
M4
Write data
Write data
Completion
to CPU No.3
to CPU No.3
device
(CPU No.3)
RST
M3
During execution of the
DDWR instruction to CPU No.3
10.1 Overview
10
867
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