Interrupts; Figure 10-9 Ebus - Sun Microsystems Netra T4 AC100 Service And System Reference Manual

The EBus channel engine also supports four DMA controllers with programmable
transfer size and chained and unchained mode. Only one device supports slave
DMA transfers on EBus: SuperI/O for the parallel port (single DMA engine).
BBC
Flash
PROM
FIGURE 10-9
10.2.4

Interrupts

The interrupt model in a Netra T4 system follows the Sun4u/Sun5 architecture.
Interrupts are delivered to the processor(s) as Mondo vectors. The CPU receives
interrupt packets that are issued over the Sun CrossBar Interconnect bus. The
processors can issue interrupts to each other (called cross-calls). They are issued by
SBC for I/O interrupts. All interrupts that are not cross-called are referred to as I/O
interrupts.
I/O interrupts are issued on separate lines by the various on-board devices, the PCI
cards, and UPA cards. The interrupts are routed to an interrupt concentrator: the
I-chip that encodes the interrupts and delivers them to the SBC. The SBC issues a
single Sun CrossBar Interconnect interrupt transaction for each active interrupt.
FIGURE 10-10
10-16 Netra T4 AC100/DC100 Service and System Reference Manual • August 2001
BootBus
I2C
JTAGS
Serial
Control
SAB
82532
TTY A
TTY B
Ebus
shows the overall interrupt organization in the Netra T4 system:
Ebus
Parallel
SuperIO
PCI (33 MHz)
PCIO-2
PHY
LU6612
Ethernet
USB
Keyboard/Mouse