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5.1.1.3
Memory Controller
The UltraSPARC T1 processor contains four independent DDR-2 memory controllers
and data interfaces. Unlike standard DDR-2 memory interfaces in the PC industry,
the UltraSPARC T1 processor uses a 144-bit datapath to main memory. Thus, the
DIMMs in a UltraSPARC T1 processor memory subsystem are always accessed two
at a time. Because each DIMM provides 64 bits of data (plus ECC), the resulting data
width is 128 bits (plus ECC).
The clock speed of the memory subsystem is nominally 200 MHz, which yields a
data bit rate of 400 Mbps using the dual data rate signaling inherent to DDR-2
SDRAM technology.
5.1.1.4
Instruction Set
The UltraSPARC T1 processor implements the standard SPARC V9 instruction set,
along with the standard UltraSPARC III extensions, including the VIS instruction set,
Interval Arithmetic support, and a special Prefetch Enhancement.
5.1.1.5
Interrupts
The UltraSPARC T1 processor follows the interrupt dispatch mechanisms laid down
in the SunV architecture. In this model, interrupts are pushed into the CPU as
Mondo Vectors which in UltraSPARC T1 systems take the form of Interrupt packets
sent over the JBus interconnect from the JBus-to-PCI-E bridge into UltraSPARC T1
processor.
5.1.1.6
UltraSPARC T1 RAS Features
For reliability, availability, and serviceability (RAS), the UltraSPARC T1 processor
provides parity protection on its internal cache memories, including tag parity and
data parity on the D-cache and I-cache. The internal 3-Mbyte L2 cache has parity
protection on the tags, and ECC protection on the data. The memory interface
provides a standard Single-bit correct, Double-bit Detect ECC protection across the
128-bits of data, for a total memory width of 144 bits. In addition, the JBus
interconnect is parity protected.
5.1.1.7
UltraSPARC T1 Processor Speed
The UltraSPARC T1 processor supports a core frequency of 1 GHz. The maximum
supported JBus speed is 200 MHz and maximum supported DDR-2 speed is 200
MHz.
5-6
Netra CP3060 Board User's Guide • April 2009
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