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Ultrasparc-Iii Processor - Sun Microsystems Netra T4 AC100 Service And System Reference Manual

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SCCR
PDB
I2C
I2C
BBC
BootGroup
Ebus
UltraSPARC III
CPU 1
E$
E$
E$
E$
Serial
Flash
Control
PROM
SAB
82532
TTYA
TTYB
FIGURE 10-1
10.2.1

UltraSPARC-III Processor

Each UltraSPARC-III processor (CPU module) implements the SPARC V-9
architecture with the Visual Instruction Set (VIS™) extension. The CPU module also
provides new VIS extensions along with prefetch instructions.
functional block diagram of the UltraSPARC-III processor.
LOM
I2C
Safari Addr/Contrl Bus
Private CPU 0 Bus
144 bits
Sun Crossbar Interconnect
Private CPU 1 Bus 144 bits
E$
E$
Interrupts
E$
E$
Ebus
Parallel
SuperIO
Netra T4 Logical System Diagram
E$
E$
E$
E$
E$
E$
E$
E$
300MHz
UltraSPARC III
CPU 0
CPMS
Private Bus
Ichip
PCIO-2
PHY
LU6612
Ethernet
USB
Chapter 10 Functional Description
Data
288 bits
Addr
Cntrl
576 bits
EPCI
SBC
PCI
SCSI
DVD-ROM
FIGURE 10-2
Memory
Subsystem
FC/AL
HUB
Hard Disks
is a
10-3

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