I2C Bus - Sun Microsystems Netra T4 AC100 Service And System Reference Manual

The multimaster I2C bus is used in the Netra T4 system to connect to the SCCR
interface. The SCCR performs a 3.3 VDC to 5 VDC voltage translation to interface
with the PDB I2C devices. The LOMlite2 module connects into the I2C bus at the
PDB and is the second I2C multimaster device.
See also Section 10.2.6, "I2C Bus" on page 10-20.
Clock Synthesizers
The BBC ASIC supports another serial interface to access the clock synthesizers.
Synthesizers allow frequency margining on the system clock.
After a power-on reset, the clock frequency for the system is set at a default low
frequency (100 MHz). The multiplier in the CPU modules also are set at their lower
value. The POST/OpenBoot PROM software determines the optimal system
frequency by reading the I2C EEPROMs on the module and the motherboard. The
POST/OpenBoot PROM software programs the new multiplier values in the CPU
processors and adjusts the frequency of the synthesizers. A subsequent reset will
activate the new multiplier values inside the processors.
Note – The Netra T4 system can accommodate two processors running at different
speeds.
10.2.6

I2C Bus

The main purposes of the I2C buses are:
Environmental control
Configuration identification
Remote system monitoring
Remote system management
At boot time, the I2C bus is used by POST and OBP to identify the current
configuration. POST and OBP access the SEEPROM on each processor board to
determine:
System configuration
CPU clock ratio
Ecache size
Processor module version
DIMM sizes
SCC contents
10-20 Netra T4 AC100/DC100 Service and System Reference Manual • August 2001