Sun Microsystems Fire V20z Management Manual page 272

TABLE H-45
POST Code
3D
41
42
45
46
47
48
49
4A
4B
4C
4E
4F
50
51
52
54
55
58
59
5A
5B
5C
60
62
64
66
67
68
69
248 Sun Fire V20z and Sun Fire V40z Servers—Server Management Guide • July 2005
BIOS POST Codes (Continued)
Description
Load alternate registers with CMOS values
Initialize extended memory for RomPilot
Initialize interrupt vectors
POST device initialization
Check ROM copyright notice
Initialize I20 support
Check video configuration against CMOS
Initialize PCI bus and devices
Initialize all video adapters in system
QuietBoot start (optional)
Shadow video BIOS ROM
Display BIOS copyright notice
Initialize MultiBoot
Display CPU type and speed
Initialize EISA board
Test keyboard
Set key click if enabled
Enable USB devices
Test for unexpected interrupts
Initialize POST display service
Display prompt "Press F2 to enter SETUP"
Disable CPU cache
Test RAM between 512KB and 640KB
Test extended memory
Test extended memory address lines
Jump to UserPatch1
Configure advanced cache registers
Initialize Multi Processor APIC
Enable external and CPU caches
Setup system management mode (SMM) area