Sun Microsystems Fire V20z Management Manual page 271

BIOS POST Codes (Continued)
TABLE H-45
POST Code Description
Initialize caches to initial POST values
0C
Initialize I/O component
0E
Initialize the local bus IDE
0F
Initialize power management
10
Load alternate registers with initial POST values
11
Restore CPU control word during warm boot
12
Initialize PCI bus mastering devices
13
Initialize keyboard controller
14
BIOS ROM checksum
16
Initialize cache before memory autosize
17
8254 programmable interrupt timer initialization
18
8237 DMA controller initialization
1A
Reset programmable interrupt controller
1C
Test DRAM refresh
20
Test 8742 keyboard controller
22
Set ES segment register to 4GB
24
Enable gate A20 line
26
Autosize DRAM
28
Initialize POST memory manager
29
Clear 512KB base RAM
2A
RAM failure on address line xxxx
2C
RAM failure on data bits xxxx of low byte of memory bus
2E
Enable cache before system BIOS shadow
2F
RAM failure on data bits xxxx of high byte of memory bus
30
Test CPU bus clock frequency
32
Initialize Phoenix Dispatch Manager
33
Warm start shut down
36
Shadow system BIOS ROM
38
Autosize cache
3A
Advanced configuration of chipset registers
3C
Appendix H Service Processor Commands 247