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High-speed counter instructions
Description for FP0, FP-e:
Bits 0–15 of the control code are allocated in groups of four, each group containing the settings for
one channel. The bit setting in each group is represented by a hex number (e.g. 0000 0000 1001
0000 = 16#90).
15
12 11
IV
Group
Channel
Clear high-speed counter instruction (bit 3)
1
0: continue
Reset input (bit 2) (see note)
2
0: enabled
Count (bit 1)
3
0: permit
Reset elapsed value to 0 (bit 0)
4
0: no
Example: 16#90
Group
Value
IV
0
III
0
II
9
I
0
Turning the reset input to TRUE, sets the elapsed value to 0. Use the reset input
setting (bit 2) to disable the reset input allocated in the system registers.
Software reset for channel 0
The first example shows how to perform a software reset for channel 0, and the second example
Example 1
shows how to perform a software reset for channel 1.
All input and output variables used for programming this function have been declared in the POU
POU header
header.
892
8
7
4
3
III
II
IV
III
3
2
1: clear
1: disabled
1: prohibit
1: yes
Description
–
–
Channel number: 1
Hex 9 corresponds to binary 1001
Clear high-speed counter instruction: clear (bit
3)
Reset input: enabled (bit 2)
Count: permit (bit 1)
Reset elapsed value to 0: yes (bit 0)
–
0
I
II
I
1
0
1
0
0
1
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