Interrupt/General Control Register - Texas Instruments MSP50C614 User Manual

3.4 Interrupt/General Control Register

The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped register
located at address 0x38. The primary component in the IntGenCtrl is the 8-bit
interrupt mask register (IMR). The service branch enable status for each of the
eight interrupts is registered in the IMR. A SET bit in the IMR enables that
interrupt to assume the service branch (at the time that the associated trigger
event occurs). A CLEAR bit disables the service branch for that interrupt. The
IMR is located at bits 0 through 7 in the IntGenCtrl. Bit 0 is associated with
INT0, which is the highest priority interrupt. Bit 7 is associated with INT7. Refer
to Section 2.7, Interrupt Logic , for more information regarding the
interrupt-system logic and initialization sequence.
IntGenCtrl register
address 0x38 (16-bit wide location)
15
CE
0x0000 : State after RESET low
CE : Comparator enable
AR : ARM bit
PD : Pulse-density clock: PDMCD
EP : Enable pullup resistors on port F
E2 : Enable TIMER2 (1 value starts timer)
E1 : Enable TIMER 1 (1 value starts timer)
S2 : Clock source for TIMER2 (0 chooses 1/2 MC)
S1 : Clock source for TIMER1 (0 chooses 1/2 MC)
The remaining bits in the IntGenCtrl have various control functions which are
not directly related to the interrupt system. Four of these are related to the timer
functions. Bits 8 and 9 are used to select the clock sources which govern the
rates of TIMER1 and TIMER2. Clearing bit 8 chooses 1/2 MC as the source
for TIMER1 (i.e., the TIMER runs at one-half the frequency of the Master
Clock). Setting bit 8 chooses the oscillator reference (RTO or CRO) as the
source for TIMER1. (The same applies for bit 9 and TIMER2.) Bits 10 and 11
in the IntGenCtrl are used to enable TIMER1 and TIMER2, respectively.
Setting bit 10 starts TIMER1, and clearing bit 10 stops TIMER1. (The same
applies for bit 11 and TIMER2).
14 13 12 11 10 09
AR PD EP E2 E1 S2
Interrupt/General Control Register
08 07 06 05 04 03
S1 D5 D4 PF D3 D2
low
priority
Interrupt mask register
D5 : port D falling-edge
5
D4 : port D rising-edge
4
D3 : port D falling-edge
3
D2 : port D rising-edge
2
PF : any port F falling-edge
T2 : TIMER2 underflow
T1 : TIMER1 underflow
DA : DAC timer underflow
(1 value enables interrupt service)
Peripheral Functions
02 01 00
T2 T1 DA
high
priority
3-17