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Video Port Control Registers
2.4.3 Video Port Interrupt Enable Register (VPIE)
The video port interrupt enable register (VPIE) enables sources of the video port interrupt to the DSP.
The video port interrupt enable register (VPIE) is shown in
31
23
22
LFDB
SFDB
R/W-0
R/W-0
15
14
Reserved
DCNA
R-0
R/W-0
7
6
LFDA
SFDA
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-5. Video Port Interrupt Enable Register (VPIE) Field Descriptions
(1)
Bit
field
symval
31-24 Reserved
-
23
LFDB
OF(value)
DEFAULT
DISABLE
ENABLE
22
SFDB
OF(value)
DEFAULT
DISABLE
ENABLE
21
VINTB2
OF(value)
DEFAULT
DISABLE
ENABLE
20
VINTB1
OF(value)
DEFAULT
DISABLE
ENABLE
19
SERRB
OF(value)
DEFAULT
DISABLE
ENABLE
18
CCMPB
OF(value)
DEFAULT
DISABLE
ENABLE
(1)
For CSL implementation, use the notation VP_VPIE_field_symval
38
Video Port
Figure 2-3. Video Port Interrupt Enable Register (VPIE)
Reserved
21
20
VINTB2
VINTB1
R/W-0
R/W-0
13
12
DCMP
DUND
R/W-0
R/W-0
5
4
VINTA2
VINTA1
R/W-0
R/W-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
Long field detected on channel B interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Short field detected on channel B interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Channel B field 2 vertical interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Channel B field 1 vertical interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Channel B synchronization error interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Capture complete on channel B interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Figure 2-3
and described in
R-0
19
18
SERRB
CCMPB
R/W-0
R/W-0
11
10
TICK
STC
R/W-0
R/W-0
3
2
SERRA
CCMPA
R/W-0
R/W-0
www.ti.com
Table
2-5.
24
17
16
COVRB
GPIO
R/W-0
R/W-0
9
8
Reserved
R-0
1
0
COVRA
VIE
R/W-0
R/W-0
SPRUEM1 – May 2007
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