Interrupt Flag Register (Ifr) - Texas Instruments TMS320C6000 Series Reference Manual

Individual Interrupt Control
Example 7–4. Code Sequence to Enable an Individual Interrupt (INT9)
Example 7–5. Code Sequence to Disable an Individual Interrupt (INT9)
7.3.2 Status of, Setting, and Clearing Interrupts
(Interrupt Flag, Set, and Clear Registers–IFR, ISR, ICR)
Figure 7–7. Interrupt Flag Register (IFR)
7-14
MVK 200h,B1 ; set bit 9
MVC IER,B0 ; get IER
OR B1,B0,B0 ; get ready to set IE9
MVC B0,IER ; set bit 9 in IER
MVK FDFFh,B1 ; clear bit 9
MVC IER,B0
AND B1,B0,B0 ; get ready to clear IE9
MVC B0,IER ; clear bit 9 in IER
The interrupt flag register (IFR) contains the status of INT4–INT15 and NMI.
Each interrupt's corresponding bit in the IFR is set to 1 when that interrupt oc-
curs; otherwise, the bits have a value of 0. If you want to check the status of
interrupts, use the MVC instruction to read the IFR. Figure 7–7 shows the IFR.
31
15
IF15 IF14 IF13 IF12 IF11
Legend: R = Readable by the MVC instruction
+0 = Cleared at reset
rsv = Reserved
The interrupt set register (ISR), shown in Figure 7–8, and the interrupt clear
register (ICR), shown in Figure 7–9, allow you to set or clear maskable inter-
rupts manually in the IFR. Writing a 1 to IS4–IS15 of the ISR causes the corre-
sponding interrupt flag to be set in the IFR. Similarly, writing a 1 to a bit of the
ICR causes the corresponding interrupt flag to be cleared. Writing a 0 to any
bit of either the ISR or the ICR has no effect. Incoming interrupts have priority
and override any write to the ICR. You cannot set or clear any bit in the ISR
or ICR to affect NMI or reset.
Reserved
R, +0
IF10 IF9 IF8 IF7 IF6
R, +0
IF5 IF4 NMIF
Rsv Rsv
16
0
0