Interrupt Set Register (Isr); Interrupt Clear Register (Icr) - Texas Instruments TMS320C6000 Series Reference Manual

Figure 7–8. Interrupt Set Register (ISR)
Figure 7–9. Interrupt Clear Register (ICR)
Example 7–6. Code to Set an Individual Interrupt (INT6) and Read the Flag Register
Example 7–7. Code to Clear an Individual Interrupt (INT6) and Read the Flag Register
Note:
Any write to the ISR or ICR (by the MVC instruction) effectively has one delay
slot because the results cannot be read (by the MVC instruction) in the IFR
until two cycles after the write to the ISR or ICR.
Any write to the ICR is ignored by a simultaneous write to the same bit in the
ISR.
Example 7–6 and Example 7–7 show code examples to set and clear individu-
al interrupts.
31
15
IS15 IS14 IS13 IS12 IS11
Legend: W = Writeable by the MVC instruction
Rsv = Reserved
31
15
IC15
IC14 IC13 IC12 IC11
Legend: W = Writeable by the MVC instruction
Rsv = Reserved
MVK 40h,B3
MVC B3,ISR
NOP
MVC IFR,B4
MVK 40h,B3
MVC B3,ICR
NOP
MVC IFR,B4
Reserved
IS10
IS9 IS8 IS7 IS6
W
Reserved
IC10 IC9 IC8 IC7 IC6
W
Individual Interrupt Control
IS5 IS4
Rsv Rsv Rsv
IC5 IC4
Rsv Rsv Rsv
Interrupts
16
0
Rsv
16
0
Rsv
7-15