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GPIO Registers
5.1.8 Video Port Pin Data Clear Register (PDCLR)
PDCLR is an alias of the video port pin data output register (PDOUT) for writes only and provides an
alternate means of driving GPIO outputs low. Writing a 1 to a bit of PDCLR clears the corresponding bit in
PDOUT. Writing a 0 has no effect. Register reads return all 0s.
The video port pin data clear register (PDCLR) is shown in
31
23
22
Reserved
PDCLR22
R-0
W-0
15
14
PDCLR15
PDCLR14
W-0
W-0
7
6
PDCLR7
PDCLR6
W-0
W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-9. Video Port Pin Data Clear Register (PDCLR) Field Descriptions
(1)
Bit
field
symval
31-23 Reserved
-
22
PDCLR22
OF(value)
DEFAULT
NONE
VCTL3CLR
21
PDCLR21
OF(value)
DEFAULT
NONE
VCTL2CLR
20
PDCLR20
OF(value)
DEFAULT
NONE
VCTL1CLR
19-2
PDCLR[19-2]
OF(value)
DEFAULT
NONE
VDATAnCLR
(1)
For CSL implementation, use the notation VP_PDCLR_PDCLRn_symval
162
General-Purpose I/O Operation
Figure 5-8. Video Port Pin Data Clear Register (PDCLR)
Reserved
21
20
PDCLR21
PDCLR20
W-0
W-0
13
12
PDCLR13
PDCLR12
W-0
W-0
5
4
PDCLR5
PDCLR4
W-0
W-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
Allows PDOUT22 bit to be cleared to a logic low without affecting other I/O pins
controlled by the same port.
0
No effect.
1
Clears PDOUT22 (VCTL3) bit to 0.
Allows PDOUT21 bit to be cleared to a logic low without affecting other I/O pins
controlled by the same port.
0
No effect.
1
Clears PDOUT21 (VCTL2) bit to 0.
Allows PDOUT20 bit to be cleared to a logic low without affecting other I/O pins
controlled by the same port.
0
No effect.
1
Clears PDOUT20 (VCTL1) bit to 0.
Allows PDOUT[19-2] bit to be cleared to a logic low without affecting other I/O pins
controlled by the same port.
0
No effect.
1
Clears PDOUT[n] (VDATA[n]) bit to 0.
Figure 5-8
and described in
R-0
19
18
PDCLR19
PDCLR18
W-0
W-0
11
10
Reserved
Reserved
W-0
W-0
3
2
PDCLR3
PDCLR2
W-0
W-0
www.ti.com
Table
5-9.
24
17
16
PDCLR17
PDCLR16
W-0
W-0
9
8
PDCLR9
PDCLR8
W-0
W-0
1
0
Reserved
Reserved
R-0
R-0
SPRUEM1 – May 2007
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