Mcbsp Interface Pins; Data Receive Register (Drr - Texas Instruments TMS320C6000 Reference Manual

McBSP Interface
Table 2.

McBSP Interface Pins

14 Multichannel Buffered Serial Port (McBSP)
Data is communicated to devices interfacing to the McBSP via the data transmit
(DX) pin for transmission and via the data receive (DR) pin for reception. Control
information (clocking and frame synchronization) is communicated via CLKS,
CLKX, CLKR, FSX, and FSR. The C6000 CPU communicates to the McBSP
using 32-bit-wide control registers accessible via the internal peripheral bus.
Non-32-bit write accesses to control registers can result in corrupting the control
register value. This is because undefined values are written to non-enabled
bytes. However, non-32-bit read accesses return the correct value.
Either the CPU or the DMA/EDMA controller reads the received data from the
data receive register (DRR) and writes the data to be transmitted to the data
transmit register (DXR). Data written to DXR is shifted out to DX via the transmit
shift register (XSR). Similarly, receive data on the DR pin is shifted into the
receive shift register (RSR) and copied into the receive buffer register (RBR).
RBR is then copied to DRR, which can be read by the CPU or the DMA/EDMA
controller. This allows simultaneous internal data movement and external data
communications. For information on registers, see section 11.
Pin I/O/Z
CLKR I/O/Z
CLKX I/O/Z
CLKS I
DR I
DX O/Z
FSR I/O/Z
FSX I/O/Z
Description
Receive clock
Transmit clock
External clock
Received serial data
Transmitted serial data
Receive frame synchronization
Transmit frame synchronization
SPRU580C