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GPIO Registers
5.1.4 Video Port Pin Direction Register (PDIR)
The PDIR controls the direction of IO pins in the video port for those pins set by PFUNC. If a bit is set to
1, the relevant pin or pin group acts as an output. If a bit is cleared to 0, the pin or pin group functions as
an input. The PDIR settings do not affect pins where the corresponding PFUNC bit is not set.
The video port pin direction register (PDIR) is shown in
31
23
22
Reserved
PDIR22
R-0
R/W-0
15
Reserved
R-0
7
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-5. Video Port Pin Direction Register (PDIR) Field Descriptions
(1)
Bit
field
symval
31-23 Reserved
-
22
PDIR22
OF(value)
DEFAULT
VCTL3IN
VCTL3OUT
21
PDIR21
OF(value)
DEFAULT
VCTL2IN
VCTL2OUT
20
PDIR20
OF(value)
DEFAULT
VCTL1IN
VCTL1OUT
19-17 Reserved
-
16
PDIR16
OF(value)
DEFAULT
VDATA16TO19IN
VDATA16TO19OUT
15-13 Reserved
-
(1)
For CSL implementation, use the notation VP_PDIR_field_symval
156
General-Purpose I/O Operation
Figure 5-4. Video Port Pin Direction Register (PDIR)
21
20
PDIR21
PDIR20
R/W-0
R/W-0
13
12
PDIR12
R/W-0
5
4
PDIR4
R/W-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
PDIR22 bit controls the direction of the VCTL3 pin.
0
Pin functions as input.
1
Pin functions as output.
PDIR21 bit controls the direction of the VCTL2 pin.
0
Pin functions as input.
1
Pin functions as output.
PDIR20 bit controls the direction of the VCTL1 pin.
0
Pin functions as input.
1
Pin functions as output.
0
Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
PDIR16 bit controls the direction of the VDATA[19-16] pins.
0
Pins function as input.
1
Pins function as output.
0
Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
Figure 5-4
and described in
Reserved
R-0
19
Reserved
R-0
11
Reserved
R-0
3
Reserved
R-0
www.ti.com
Table
5-5.
24
17
16
PDIR16
R/W-0
9
8
PDIR8
R/W-0
1
0
PDIR0
R/W-0
SPRUEM1 – May 2007
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