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GPIO Registers
5.1.3 Video Port Pin Function Register (PFUNC)
The video port pin function register (PFUNC) selects the video port pins as GPIO. Each bit controls either
one pin or a set of pins. When a bit is set to 1, it enables the pin(s) that map to it as GPIO. The GPIO
feature should not be used for pins that are used as part of the capture or display operation. For pins that
have been muxed out for use by another peripheral, the PFUNC bits will have no effect.
The VDATA pins are broken into two functional groups: VDATA[9-2] and VDATA[19-12]. Thus, each entire
half of the data bus must be configured as either functional pins or GPIO pins. In the case of single
BT.656 or raw 8-bit mode, the upper 10 VDATA pins (VDATA[19-12]) can be used as GPIOs. If the video
port is disabled, all pins can be used as GPIO.
The video port pin function register (PFUNC) is shown in
31
23
22
Reserved
PFUNC22
R-0
R/W-0
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-4. Video Port Pin Function Register (PFUNC) Field Descriptions
(1)
Bit
field
symval
31-23 Reserved
-
22
PFUNC22
OF(value)
DEFAULT
NORMAL
VCTL3
21
PFUNC21
OF(value)
DEFAULT
NORMAL
VCTL2
20
PFUNC20
OF(value)
DEFAULT
NORMAL
VCTL1
19-11 Reserved
-
(1)
For CSL implementation, use the notation VP_PFUNC_field_symval
154
General-Purpose I/O Operation
Figure 5-3. Video Port Pin Function Register (PFUNC)
Reserved
21
20
PFUNC21
PFUNC20
R/W-0
R/W-0
Reserved
R-0
Reserved
R-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
PFUNC22 bit determines if VCTL3 pin functions as GPIO.
0
Pin functions normally.
1
Pin functions as GPIO pin.
PFUNC21 bit determines if VCTL2 pin functions as GPIO.
0
Pin functions normally.
1
Pin functions as GPIO pin.
PFUNC20 bit determines if VCTL1 pin functions as GPIO.
0
Pin functions normally.
1
Pin functions as GPIO pin.
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
Figure 5-3
and described in
R-0
19
11
10
PFUNC10
R/W-0
www.ti.com
Table
5-4.
24
16
Reserved
R/W-0
9
8
Reserved
R-0
1
0
PFUNC0
R/W-0
SPRUEM1 – May 2007
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