Interlaced Raw Display Example; Bt.656 Interlaced Display Vertical Timing Example - Texas Instruments TMS320DM648 User Manual

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Figure 4-26. BT.656 Interlaced Display Vertical Timing Example
A Assumes VCT1P bit in VPCTL is set to 1 (active-low output). VSYNC output when VCTL2S bit in VDCTL is set to 00,
VBLNK output when VCTL2S bit is set 01.
B If DVEN bit in VDCTL is set to 1; otherwise, blanking value is output.

4.9.2 Interlaced Raw Display Example

This section shows an example of raw display output for the same 704 x 408 interlaced image.
The horizontal output timing is shown in
pipeline delay between the internal counter changing and the output on external pins. The actual delay
can be longer or shorter as long as it is consistent within any display mode. The active line is 720-pixels
wide. Figure 4-27 shows the 704-pixel image window centered in the screen that results in an IMGHOFFx
of 8 pixels.
The HBLNK and HSYNC signals are shown as they would be output for active-low operation. Note that
only one of the two signals is actually available externally. The HBLNK inactive edge occurs on sample 0.
The IPCOUNT operation follows the description in
displayed pixel (FPCOUNT = IMGHOFFx) and stops counting at the last displayed pixel (IPCOUNT =
IMGHSIZEx). Both the IPCOUNT and FPCOUNT counters increment on every third VCLKIN rising edge,
as programmed by the INCPIX bits in VDTHRLD with a value of 3.
VDOUT shows the output data and switching between Default Data, and FIFO Data. Three values are
output sequentially on VDOUT for each pixel count. Note that the default value is output during both the
blanking and non-display image active video regions.
SPRUEM1 – May 2007
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EAV
FLCOUNT ILCOUNT V F
525 240 0
1 240 1
2 240 1
3 240 1
4 240 1
Field 1 blanking
5 240 1
6 240 1
19 240 1
20 240 0
21 Field 1 active 240 0
22 240 0
23 1 0
2 0
Field 1 image
239 0
262 240 0
263 240 0
264 240 1
265 240 1
266 240 1
267 240 1
Field 2 blanking
268 240 1
269 240 1
282 240 1
283 240 0
284 Field 2 active 240 0
285 240 0
286 1 0
2 0
Field 2 image
524 239 0
525 240 0
1 240 1
240 1
IMGVOFF1 = 3 VBLNKXSTART1 = 720
IMGVSIZE1 = 240 VBLNKYSTART1 = 1
IMGVOFF2 = 3 VBLNKXSTOP1 - 720
IMGVSIZE2 = 240 VBLNKYSTOP1 - 20
FRMHEIGHT = 525 VBLNKXSTAR2 = 360
VBITSET1 = 1 VBLNKYSTART2 = 263
VBITCLR1 = 20 VBLNKXSTOP2 = 360
VBITSET2 = 264 BLNKYSTOP2 = 283
VBITCLR2 = 283
Figure
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
VSYNCXSTART1 = 720 FLD1XSTART = 720
VSYNCYSTART1 = 4 FLD1YSTART = 1
VSYNCXSTOP1 = 720 FLD2XSTART = 360
VSYNCYSTOP1 = 7 FLD2YSTART = 263
VSYNCXSTART2 = 360
VSYNCYSTART2 = 266 FBITSET = 266
VSYNCXSTOP2 = 360 FBITCLR = 4
VSYNCYSTOP2 = 269
4-27. This diagram assumes that there is a two VCLK
Section 4.1.2. IPCOUNT resets to 0 at the first
Display Timing Examples
Active
horizontal
output
Blanking value
Blanking value
Blanking value
Blanking value
Blanking value
Blanking value
Blanking value
Blanking value
Default value§
Default value§
Default value§
FIFO data
FIFO data
FIFO data
FIFO data
Default value§
Blanking value
Blanking value
Blanking value
Blanking value
Blanking value
Blanking value
Blanking value
Default value§
Default value§
Default value§
FIFO data
FIFO data
FIFO data
FIFO data
Blanking value
Blanking value
Video Display Port 113