Frame Phases; Number Of Phases, Words, And Bits Per Frame; Single-Phase Frame Example; Mcbsp Register Bits That Determine The Number Of Phases, Words, And Bits Per Frame - Texas Instruments TMS320VC5501 Reference Manual

2.4 Frame Phases

2.4.1

Number of Phases, Words, and Bits Per Frame

Table 2−1. McBSP Register Bits That Determine the Number of Phases, Words, and
Bits Per Frame
Operation
Reception
Reception
Transmission
Transmission
2.4.2

Single-Phase Frame Example

SPRU592E
The McBSP allows you to configure each frame to contain one or two phases.
The number of words per frame, and the number of bits per word, can be
specified differently for each of the two phases of a frame, allowing greater
flexibility in structuring data transfers. For example, a user might define a
frame as consisting of one phase containing two words of 16 bits each,
followed by a second phase consisting of 10 words of 8 bits each. This
configuration permits the user to compose frames for custom applications, or
in general, to maximize the efficiency of data transfers.
Table 2−1 shows which bit fields in the receive control registers (RCR1 and
RCR2) and in the transmit control registers (XCR1 and XCR2) determine the
number of phases per frame, the number of words per frame, and number of
bits per word for each phase, for the receiver and transmitter. The maximum
number of words per frame is 128 for a single-phase frame and 256 for a
dual-phase frame. The number of bits per word can be 8, 12, 16, 20, 24, or 32
bits. The maximum number of bits (serial port clock cycles) per frame is 4096.
Number of Phases
1 (RPHASE = 0)
2 (RPHASE = 1)
1 (XPHASE = 0)
2 (XPHASE = 1)
Figure 2−7 shows an example of a single-phase data frame comprising one
8-bit word. Since the transfer is configured for one data bit delay, the data on
the DX and DR pins are available one clock cycle after FS(R/X) goes active.
The figure makes the following assumptions:
(R/X)PHASE = 0: Single-phase frame
-
(R/X)FRLEN1 = 0b: 1 word per frame
-
Words Per Frame
Set With ...
RFRLEN1
RFRLEN1 and
RFRLEN2
XFRLEN1
XFRLEN1 and
XFRLEN2
McBSP Operation
Frame Phases
Bits Per Word
Set With ...
RWDLEN1
RWDLEN1 for phase 1
RWDLEN2 for phase 2
XWDLEN1
XWDLEN1 for phase 1
XWDLEN2 for phase 2
2-11