Device-Level Advisories; Dl_2 Software Modification Of Mpnmc Bit Is Not Pipeline-Protected; Dl_7 Reti Instruction May Affect The Xf State - Texas Instruments TMS320VC5509A Manual

TMS320VC5509A Silicon Errata
3.2

Device-Level Advisories

Advisory DL_2
Revision(s) Affected:
Details:
Assembler Notification: None
Workaround:
Advisory DL_7
Revision(s) Affected:
Details:
Assembler Notification: None
Workaround:
1.0 and 1.1
Software modification of the MPNMC bit in status register 3 (ST3_55) is not pipeline-protected
so changes to the device memory map may not become valid before the instructions that
immediately follow the modification.
Insert six NOPs after the MPNMC modification.
1.0 and 1.1
The XF pin state is saved on the stack as a part of the ST1 context saving during interrupts
servicing. If the XF pin state is changed inside the ISR, upon execution of the RETI, the XF bit
will be restored to the value prior to entering the ISR. If XF state is not changed inside the ISR,
then there is no issue.
BIOS takes care of this problem with software workaround, which is transparent to the users.
Non-BIOS users who are changing XF pin state in an ISR should also modify the ST1 value
on the stack to maintain the correct XF pin state upon exiting the ISR.
Software Modification of MPNMC Bit is Not Pipeline-Protected
RETI Instruction may Affect the XF State
SPRZ200E
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