Mcbsp Module With Fifo - Texas Instruments SM320F2812-HT Data Manual

SM320F2812-HT
SGUS062B – JUNE 2009 – REVISED JUNE 2011
Figure 4-9 shows the block diagram of the McBSP module with FIFO, interfaced to the F2812 version of
Peripheral Frame 2.
MXINT
TX Interrupt Logic
To CPU
McBSP Transmit
Interrupt Select Logic
LSPCLK
McBSP Registers
and Control Logic
McBSP Receive
Interrupt Select Logic
RX Interrupt Logic
MRINT
To CPU
68 Peripherals
TX FIFO
Interrupt
DXR2 Transmit Buffer
McBSP
DRR2 Receive Buffer
RX FIFO
Interrupt
Figure 4-9. McBSP Module With FIFO
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Peripheral Write Bus
TX FIFO _15 TX FIFO _15
— —
TX FIFO _1 TX FIFO _1
TX FIFO _0 TX FIFO _0
TX FIFO Registers
16
DXR1 Transmit Buffer
16
Compand Logic
XSR2 XSR1
RSR1
RSR2
16
16
Expand Logic
RBR2 Register RBR1 Register
16
16
DRR1 Receive Buffer
16 16
RX FIFO _15 RX FIFO _15
— —
RX FIFO _1 RX FIFO _1
RX FIFO _0 RX FIFO _0
RX FIFO Registers
Peripheral Read Bus
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SM320F2812-HT
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16
FSX
16
CLKX
DX
DR
CLKR
FSR