Mdio; Figure 9. Tlk3134 Evm Mdio Connector (Jmp22) - Texas Instruments TLK3134 XAUI User Manual

Transceiver / 4 channel multi-rate transceiver evaluation module
Hide thumbs Also See for TLK3134 XAUI:
Table of Contents

Advertisement

MDIO

The TLK3134 supports the Management Data Input/Output (MDIO) Interface as defined in Clauses 22
and 45 of the IEEE 802.3ae Ethernet Specification. The MDIO allows register-based management and
control of the serial links. Normal operation of the TLK3134 is possible without the use of this interface,
however, some additional features are accessible only through this interface.
The MDIO Management Interface consists of a bi-directional data path (MDIO) and a clock reference
(MDC). The device ID and port address are determined by control pins PRTAD[4:0]. The ST pin
controls whether the device responds as a Clause 22 or Clause 45 device.
In Clause 45 (ST=0), the top 4 control pins PRTAD[4:1] determine the device port address. In Clause
45 mode the TLK3134 can be accessed only through even port addresses. In this mode, the TLK3134
will respond if the PHY address field on the MDIO protocol (PA[4:0]) matches {PRTAD[4:1], 1'b0}. The
PRTAD[0] pin acts as a device ID pin where it determines whether the TLK3134 is a DTE or PHY
device and is required to be either 4 (PHY) or 5 (DTE), so only one bit is required to differentiate. If
PRTAD[0] is a 0, then a PHY device is selected for the XGXS. If PRTAD[0] is a 1, then a DTE device is
selected for the XGXS. In this mode, TLK3134 will respond as PHY if the Device address field
(DA[4:0]) on the MDIO protocol is 5'b00100 and as DTE if it is 5'b00101. Note, each register is
accessed as either DTE or PHY devices in the TLK3134, although physically there is only one register
accessed two different ways.
In Clause 22 (ST= 1), the top 3 control pins PRTAD[4:2] determine the device port address. In this
mode the 4 individual channels in TLK3134 are classified as 4 different ports. So for any PRTAD[4:2]
value there will be 4 ports per TLK3134. The TLK3134 will respond if the 3 MSB's of PHY address field
on MDIO protocol (PA[4:2]) matches PRTAD[4:2]. The 2 LSB's of PHY address field (PA[1:0]) will
determine which channel/port within the TLK3134 to respond.
If PA[1:0] = 2'b00, TLK3134's Channel 0 will respond.
If PA[1:0] = 2'b01, TLK3134's Channel 1 will respond.
If PA[1:0] = 2'b10, TLK3134's Channel 2 will respond.
If PA[1:0] = 2'b11, TLK3134's Channel 3 will respond.
Write transactions to invalid registers or read only registers will be ignored. Read transactions of invalid
registers will return a "0".
The bi-directional MDIO pin is pulled up to 1.2V or 2.5V (VDDM) with a 1.5k Ω resistor as per the MDIO
Standard.
16
TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users' Guide
SLLU104A - September 2007
Figure 9.
TLK3134 EVM MDIO Connector (JMP22)
MDIO
GND
MDC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
JMP22

Advertisement

Table of Contents
loading

Table of Contents