NCLK
2
RESET
MPU
MPU
COUNTER
RESET
NSD
NSD
FF1
FF2
NAND
2–68
m
I
sec
DIVIDE BY
59700
59.7 Msec
4
2
P2
RESET
DECODE 96
16
64
T0
T1
ENERGIZE
RELAY
Figure 2–44. Motor Relay Trigger Circuit, P600
FF1
238.8
–
Msec
Q
CLR
MPU
119.4
RESET
Msec
FF2
Q
–
Q
CLR
m
119.4
sec
P300/P600 Principles of Operation
+5V
NAND
CLOCK
COUNTER
RESET
T2
UP TO SPEED
DE–ENERGIZE
RELAY
+
RELAY
–
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