Hammer Reset Timer - Printronix p300 Maintenance Manual

2–5. Print State
h. Hammer Reset Timer, P600 Only (Figure 2–15)
The hammer reset timer minimizes energy use in the hammer bank by adjusting the current flow time in-
terval relative to the number of hammer coils to be energized. The current flow interval is the time between
the rise of OE and the generation of NHRSH, with a range between 176 and 258.5 microseconds.
OE is set when NHCK loads the hammer driver shift register into the data latches. The timing of NHRSH is
controlled by the hammer reset timer in the following way:
COMH line data bits are shifted into the input latch one bit at a time by NHSCH. For a logical 1
data bit, the latch is set and bit counter FF3 increments one count. The counter does not increment
if the data bit is a 0. After the 66 data bits have been evaluated by the latch, NSYNCH loads the
accumulated bit count into down counter FF2. During the transfer, the least significant bit posi-
tion is lost, dividing the count by 2; i.e. a bit count of 66 becomes 33 in the down counter.
352 CLK counts (176 microseconds) after OE, N160H sets the delay flip–flop KK2, enabling the 2.5 mi-
crosecond clock (2.5 CKI). The down counter is then decremented until its count underflows, resetting
hammer reset flip–flop KK2 and generating NHRSH.
COMH
D
DATA
LATCH
Q –
NHSCH
C
CLR
(.5 usec)
NCLKH
DELAY
N160H
FLIP
FLOP
KK2 Q –
176
(176 usec)
m
sec
NSYNCH
NHSCH
NCLK
1
COMH
DATA
1
LATCH
NSYNCH
P300/P600 Principles of Operation
–continued
MSB
BIT
COUNTER
FF3
LSB
5
CLOCK
ENABLE
(2.5 usec)
2.5 CK1
2 3 4
2 3 4
Figure 2–15. Hammer Reset Timer, P600
MSB
DOWN
COUNTER
FF2
CLK
LSB
LD
CLR
J
Q
–
Q
CLR
n = NUMBER OF LOGIC 1 BITS
5 6
5 6
N160H+
NSYCH
'
(N
t t
m
sec
TI T2 T3
HRS Q
FLIP FLOP
Q
KK2
T1=NSYNCH
T2=N160H
m
T3=N160H + (2.5n) SEC
t t
t t
n
t t
t t
n
t t
2–25
2.5)
NHRSH