Overlap In Chip-Select Ranges; Programming Model; System Control Register (Scr) - Motorola DragonBall MC68328 User Manual

2.1.2.2 OVERLAP IN CHIP-SELECT RANGES. Users
programming the group address and chip-select registers. If they are programmed to
overlap, the CS signals will overlap.
Unused chip-selects must be programmed to 0 wait states and
16-bit width. Map them to dummy space, if possible.
When the CPU attempts to write to a read-only location, as programmed by users when
setting up the chip-selects, the chip-select signal is not asserted, no DTACK is asserted and
BERR is asserted if the bus-error timer is enabled.
The chip-select logic does not allow an address match during in-
terrupt-acknowledge (Function Code 7) cycles.
The programming of the chip-select module is discussed later in this chapter. For additional
information, refer to 2.5 Chip-Select Registers .

2.2 PROGRAMMING MODEL

The various modules in the MC68328 processor, including the SIM28, contain registers that
control the modules and provide status information from the modules. All of these registers
reside in the top 4096-byte range ($FFFFF000 to $FFFFFFFF) of addresses in the memory
map of the MC68EC000 core processor. It is also doubly mapped at $FFF000 to $FFFFFF
from reset.

2.2.1 System Control Register (SCR)

The SCR can be read or written at any time by 8-bit or 16-bit transfers. An 8-bit read/write
location, it resides at address hex $FFF000 or $FFFFF000 in supervisor data space. The
SCR cannot be accessed in user data space if the supervisor-only bit (SO) is set. The SO
bit is set to 1 after reset. The register consists of 3 status bits and 4 system-control bits. The
bus-error timeout (BETO) status bit is normally 0 and is set to 1 by a bus timeout event in
the system. Writing a 0 to these bits has no effect; writing a 1 clears the status bit.
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
NOTE
NOTE
7 6 5 4
BETO WPV PRV BETEN
Address: $(FF)FFF000
Figure 2-3. System Control Register
System Integration Module
should
3 2 1 0
SO DMAP RSVD WDTH8
Reset Value: $0C
take care when
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