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SPI-Master
• Wait for interrupt or poll SPMIRQ bit
For systems that need more than 16 clocks to transfer data, the SPMEN bit can remain
asserted between exchanges. The enable signal needed in some SPI slave devices should
be provided by an I/O port bit.
10.2.2 Phase/Polarity Configurations
The SPIM transfers data in and out of the shift register with the SPICLK. Data is clocked
using any one of the variations of clock phase and clock polarity. The clocked transfer may
be programmed in phase and in polarity (Figure 10-2). In phase 0 operation, output data
changes on falling clock edges, while input data is shifted on rising edges. In a phase 1
operation, output data changes on rising edges of the clock and is shifted on falling edges.
Polarity = 1 inverts the data-clock relationships. This flexibility allows operation with most
serial peripheral devices on the market.
10.3 SIGNAL DESCRIPTIONS
The following signals are multiplexed with other signals in port K. Refer to Section 7.1.10
for more information.
10-2
MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
(POL=1, PHA=1)
SPMCLK
(POL=1, PHA=0)
SPMCLK
(POL=0, PHA=1)
SPMCLK
SPMCLK
(POL=0, PHA=0)
SPMTxD
SPMRxD
Figure 10-2. Master SPI Operation
B
B
B
B
...
...
N-1
N-2
N-3
N
B
B
B
B
...
...
N-2
N-1
N-3
N
B
B
1
0
B
B
1
0
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