UG-180
CP Gain Operation................................................................... 105
Features of Manual Gain Control ...................................... 105
Features of Automatic Gain Control ................................. 105
Manual Gain and Automatic Gain Control Selection..... 105
Manual Gain Control........................................................... 106
Manual Gain Filter Mode.................................................... 108
Other Gain Controls ............................................................ 108
CP Offset Block......................................................................... 109
Notes ...................................................................................... 109
AV Code Block.......................................................................... 110
CP Data Path for HDMI Modes ............................................. 112
Pregain Block ........................................................................ 112
Sync Processed by CP Section ................................................ 115
Sync Routing from HDMI Section .................................... 115
Standard Detection and Identification.............................. 115
Detailed Mechanism of STDI Block Horizontal/Vertical
Lock Mechanism .................................................................. 118
CP Output Synchronization Signal Positioning................... 122
CP Synchronization Signals ................................................ 124
HSync Timing Controls ...................................................... 124
VSync Timing Controls....................................................... 126
DE Timing Controls ............................................................ 128
FIELD Timing Controls ...................................................... 129
HCOUNT Timing Control ................................................. 133
CP HDMI Controls.................................................................. 134
Free Run Mode ......................................................................... 134
Free Run Mode Thresholds................................................. 134
Free Run Feature in HDMI Mode...................................... 136
Free Run Default Color Output.......................................... 137
CP Status.................................................................................... 138
CP_REG_FF.......................................................................... 138
CP Core Bypassing.................................................................... 138
Consumer Electronics Control ................................................... 139
Main Controls ........................................................................... 139
CEC Transmit Section ............................................................. 140
CEC Receive Section................................................................ 142
Logical Address Configuration .......................................... 142
Receive Buffers...................................................................... 143
CEC Message Reception Overview.................................... 146
Antiglitch Filter Module .......................................................... 147
Typical Operation Flow ........................................................... 148
Initializing CEC Module ..................................................... 148
Using CEC Module as Initiator .......................................... 149
Using CEC Module as Follower ......................................... 150
Low Power CEC Message Monitoring................................... 151
Interrupts....................................................................................... 153
Interrupt Architecture Overview ........................................... 153
Interrupt Pins............................................................................ 156
Notes ...................................................................................... 156
Interrupt Duration ............................................................... 157
Interrupt Drive Level ........................................................... 157
Interrupt Manual Assertion................................................ 157
Multiple Interrupt Events.................................................... 158
Description of Interrupt Bits .................................................. 159
General Operation ............................................................... 159
HDMI Video Mode.............................................................. 159
CEC ........................................................................................ 159
HDMI Only Mode ............................................................... 159
Additional Explanations.......................................................... 160
STDI_DATA_VALID_RAW............................................... 160
CP_LOCK, CP_UNLOCK ................................................. 161
HDMI Interrupts Validity Checking Process................... 161
Storing Masked Interrupts .................................................. 163
Register Access and Serial Ports Description ........................... 174
2
Main I
C Port ............................................................................ 174
Register Access ..................................................................... 174
2
IO I
C Map Address............................................................. 174
Addresses of Other Maps .................................................... 175
Protocol for Main I
DDC Ports................................................................................. 177
2
I
C Protocols for Access to the Internal EDID................. 177
2
I
C Protocols for Access to HDCP Registers.................... 177
DDC Port A .......................................................................... 177
Appendix A ................................................................................... 178
PCB Layout Recommendations ............................................. 178
Power Supply Bypassing .......................................................... 178
Example of a Current Loop................................................. 178
Digital Outputs (Data and Clocks) ........................................ 178
Digital Inputs ............................................................................ 179
XTAL and Load Cap Value Selection .................................... 179
Example ................................................................................. 179
Rev. A | Page 4 of 184
Hardware User Guide
2
C Port.................................................. 176
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