Analog Devices Advantiv ADV7611 Hardware User's Manual page 163

Hardware User Guide
Storing Masked Interrupts
STORE_UNMASKED_IRQS , IO, Address 0x40[4]
STORE_MASKED_IRQS allows the HDMI status flags for any HDMI interrupt to be triggered regardless of whether the mask bits are
set. This bit allows a HDMI interrupt to trigger and allows this interrupt to be read back through the corresponding status bit without
triggering an interrupt on the interrupt pin. The status is stored until the clear bit is used to clear the status register and allows another
interrupt to occur.
Function
STORE_UNMASKED_IRQS
0 (default)
1
List of Interrupt Status Registers
INTERRUPT_STATUS_1 register consists of fields: STDI_DATA_VALID_ST, CP_UNLOCK_ST, and CP_LOCK_ST.
STDI_DATA_VALID_ST , IO, Address 0x43[4] (Read Only)
Latched signal status of STDI valid interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
STDI_DATA_VALID_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
STDI_DATA_VALID_ST
0 (default)
1
CP_UNLOCK_ST , IO, Address 0x43[3] (Read Only)
Latched signal status of CP Unlock interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
CP_UNLOCK_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
CP_UNLOCK_ST
0 (default)
1
CP_LOCK_ST , IO, Address 0x43[2] (Read Only)
Latched signal status of the CP lock interrupt signal. Once set, this bit will remain high until the interrupt is cleared via CP_LOCK_CLR.
This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
CP_LOCK_ST
0 (default)
1
INTERRUPT_STATUS_2 register consists of one field: MPU_STIM_INTRQ_ST.
MPU_STIM_INTRQ_ST , IO, Address 0x48[7] (Read Only)
Latched signal status of manual forced interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
MPU_STIM_INTRQ_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
MPU_STIM_INTRQ_ST
0 (default)
1
Description
Does not allow x_ST flag of any HDMI interrupt to be set independently of mask bits
Allows x_ST flag of any HDMI interrupt to be set independently of mask bits
Description
No STDI valid interrupt has occurred.
A STDI valid interrupt has occurred.
Description
No CP UNLOCK interrupt event has occurred.
A CP UNLOCK interrupt event has occurred.
Description
No CP LOCK interrupt event has occurred.
A CP LOCK interrupt event has occurred.
Description
Forced manual interrupt event has not occurred.
Force manual interrupt even has occurred.
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