Analog Devices Advantiv ADV7611 Hardware User's Manual page 35

Hardware User Guide
Function
VIDEO_3D_RAW
0
1
TMDS MEASUREMENT
The ADV7611 contains logic that measures the frequency of the TMDS clock transmitted. The TMDS frequency can be read back via the
TMDSFREQ[8:0] and TMDSFREQ_FRAC[6:0]
TMDS Measurement after TMDS PLL
The TMDSFREQ measurement is provided by a clock measurement circuit located after the TMDS PLL. The TMDS PLL must, therefore,
be locked to the incoming TMDS clock in order for the TMDSFREQ and TMDSFREQ_FRAC registers to return a valid measurement.
The TMDS frequency can be obtained using Equation 1, TMDS Frequency in MHz (Measured after TMDS PLL).
 
F TMDSFREQ
TMDS
Notes

The TMDS PLL lock status can be monitored via TMDS_PLL_LOCKED.

The TMDS_PLL_LOCKED flag should be considered valid if a TMDS clock is input on the HDMI port selected via
HDMI_PORT_SELECT[2:0].

The NEW_TMDS_FRQ_RAW
programmable threshold.
The ADV7611 can be configured to trigger an interrupt when the bit
configuration, the interrupt status
Interrupts section for additional information on the configuration of interrupts.
TMDSFREQ[8:0] , Addr 68 (HDMI), Address 0x51[7:0]; Address 0x52[7] (Read Only)
This register provides a full precision integer TMDS frequency measurement.
Function
TMDSFREQ[8:0]
000000000 (default)
xxxxxxxxx
TMDSFREQ_FRAC[6:0] , Addr 68 (HDMI), Address 0x52[6:0] (Read Only)
A readback to indicate the fractional bits of measured frequency of PLL recovered TMDS clock. The unit is 1/128 MHz.
Function
TMDSFREQ_FRAC[6:0]
0000000 (default)
xxxxxxx
TMDS_PLL_LOCKED , Addr 68 (HDMI), Address 0x04[1] (Read Only)
A readback to indicate if the TMDS PLL is locked to the TMDS clock input to the selected HDMI port.
Function
TMDS_PLL_LOCKED
0 (default)
1
TMDSPLL_LCK_A_RAW , IO, Address 0x6A[6] (Read Only)
A readback to indicate the raw status of the Port A TMDS PLL lock signal.
Function
TMDSPLL_LCK_A_RAW
0 (default)
1
Description
Video 3D not detected (read only)
Video 3D detected
registers.
TMDSFREQ _ FRAC
128
flag can be used to monitor if the TMDS frequency on the selected HDMI port changes by a
NEW_TMDS_FRQ_ST
Description
Outputs 9-bit TMDS frequency measurement in MHz
Outputs 9-bit TMDS frequency measurement in MHz
Description
Outputs 7-bit TMDS fractional frequency measurement in 1/128 MHz
Outputs 7-bit TMDS fractional frequency measurement in 1/128 MHz
Description
The TMDS PLL is not locked.
The TMDS PLL is locked to the TMDS clock input to the selected HDMI port.
Description
TMDS PLL on Port A is not locked.
TMDS PLL on Port A is locked to the incoming clock.
(1)
NEW_TMDS_FRQ_RAW
indicates that NEW_TMDS_FRQ_RAW
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changes from 0 to 1. In that
has changed from 0 to 1. Refer to the
UG-180