Analog Devices Advantiv ADV7611 Hardware User's Manual page 156

UG-180
NEW AVI INFOFRAME
DETECTION
INTERNAL PULSE FLAG
NEW_AVI_INFO_RAW
NEW_AVI_INFO_ST
In this section, all raw bits are classified as being triggered by either level sensitive or edge sensitive events, with the following
understanding of the terminology
•
Level sensitive events are events that are generally either high or low and are not expected to change rapidly. The raw bit for level
sensitive events is not latched and therefore always represents the true real-time status of the event in question.
•
Edge sensitive events are events that only exist for an instant. The raw bits for edge sensitive events are latched and therefore
represent the occurrence of an edge sensitive event that happened in the past. Raw bits for edge sensitive events must be cleared by
the corresponding clear bit.
INTERRUPT PINS
The ADV7611 features two dedicated interrupt pins, INT1 and INT2. INT1 is always enabled, but INT2 is disabled by default and must
be enabled using the following I
INTRQ2_MUX_SEL[1:0] , IO, Address 0x41[1:0]
Interrupt signal configuration control for INT2
Function
INTRQ2_MUX_SEL[1:0]
00 (default)
01
10
11
Notes
•
INT1 is in a high impedance state after reset as the ADV7611 resets with open drain enabled on INT1.
•
The ADV7611 resets with the INT2 disabled. The
INT2 function on the one of the pins: MCLK/INT2, SCLK/INT2, HPA_A/INT2.
•
The ADV7611 resets with all interrupts masked off on INT1 and INT2.
•
An interrupt is enabled for a specific event by masking the corresponding mask bit in the IO map.
AVI INFOFRAME WITH
NEW CONTENT DETECT
TIME > 2XTAL PERIODS
TIME TAKEN BY
THE CPU TO CLEAR
NEW_AVI_INFO_ST
Figure 64. NEW_AVI_INFO_RAW and NEW_AVI_INFO_ST Timing
2
C control.
INTRQ2_MUX_SEL[1:0]
Rev. A | Page 156 of 184
NEW_AVI_INFO_CLR
SET TO 1
Description
INT2 disabled
INT2 in MCLK/INT2 pin
INT2 in SCLK/INT2 pin
INT2 in HPA_A/INT2 pin
bit in the IO Map must be set in order to enable the
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