Analog Devices Advantiv ADV7611 Hardware User's Manual page 38

UG-180
DCFIFO_KILL_DIS , Addr 68 (HDMI), Address 0x1B[2]
The video FIFO output is zeroed if there is more than one resynchronization of the pointers within two FIFO cycles. This behavior can be
disabled with this bit.
Function
DCFIFO_KILL_DIS
0 (default)
1
DCFIFO_KILL_NOT_LOCKED , Addr 68 (HDMI), Address 0x1B[3]
DCFIFO_KILL_NOT_LOCKED controls whether or not the output of the Video FIFO is set to zero when the video PLL is unlocked.
Function
DCFIFO_KILL_NOT_LOCKED
0
1 (default)
The DCFIFO is programmed to reset itself automatically when the video PLL transitions from unlocked to locked. Note that the video
PLL transition does not necessarily indicate that the overall system is stable.
DCFIFO_RESET_ON_LOCK , Addr 68 (HDMI), Address 0x1B[4]
Enables the reset/recentering of video FIFO on video PLL unlock
Function
DCFIFO_RESET_ON_LOCK
0
1 (default)
PIXEL REPETITION
In HDMI mode, video formats with TMDS rates below 25 M pixels/sec require pixel repetition in order to be transmitted over the TMDS
link. When the ADV7611 receives this type of video format, it discards repeated pixel data automatically, based on the pixel repetition
field available in the AVI InfoFrame.
When HDMI_PIXEL_REPETITION is nonzero, video pixel data is discarded and the pixel clock frequency is divided by
(HDMI_PIXEL_REPETITION) + 1.
HDMI_PIXEL_REPETITION[3:0] , Addr 68 (HDMI), Address 0x05[3:0] (Read Only)
A readback to provide the current HDMI pixel repetition value decoded from the AVI InfoFrame received. The HDMI receiver
automatically discards repeated pixel data and divides the pixel clock frequency appropriately as per the pixel repetition value.
Function
HDMI_PIXEL_REPETITION[3:0]
0000 (default)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010 to 1111
Description
FIFO output set to zero if more than one resynchronization is necessary during two FIFO cycles
FIFO output never set to zero regardless of how many resynchronizations occur
Description
FIFO data is output regardless of video PLL lock status.
FIFO output is zeroed if video PLL is unlocked.
Description
Do not reset on video PLL lock
Reset FIFO on video PLL lock
Description
1×
2×
3×
4×
5×
6×
7×
8×
9×
10×
Reserved
Rev. A | Page 38 of 184
Hardware User Guide