Analog Devices Advantiv ADV7611 Hardware User's Manual page 167

Hardware User Guide
Function
TMDSPLL_LCK_A_ST Description
0 (default) TMDSPLL_LCK_A_RAW has not changed. An interrupt has not been generated.
1 TMDSPLL_LCK_A_RAW has changed. An interrupt has been generated.
TMDS_CLK_A_ST , IO, Address 0x6B[4] (Read Only)
Latched status of Port A TMDS clock detection interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
TMDS_CLK_A_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
TMDS_CLK_A_ST Description
0 (default) TMDS_CLK_A_RAW has not changed. An interrupt has not been generated.
1 TMDS_CLK_A_RAW has changed. An interrupt has been generated.
VIDEO_3D_ST , IO, Address 0x6B[2] (Read Only)
Latched status for the video 3D interrupt. Once set, this bit will remain high until the interrupt is cleared via VIDEO_3D_CLR. This bit is
only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
VIDEO_3D_ST Description
0 (default) VIDEO_3D_RAW has not changed. An interrupt has not been generated.
1 VIDEO_3D_RAW has changed. An interrupt has been generated.
V_LOCKED_ST , IO, Address 0x6B[1] (Read Only)
Latched status for the vertical sync filter locked interrupt. Once set, this bit will remain high until the interrupt is cleared via
V_LOCKED_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
V_LOCKED_ST Description
0 (default) V_LOCKED_RAW has not changed. An interrupt has not been generated.
1 V_LOCKED_RAW has changed. An interrupt has been generated.
DE_REGEN_LCK_ST , IO, Address 0x6B[0] (Read Only)
Latched status for DE regeneration lock interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
DE_REGEN_LCK_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
DE_REGEN_LCK_ST Description
0 (default) DE_REGEN_LCK_RAW has not changed. An interrupt has not been generated.
1 DE_REGEN_LCK_RAW has changed. An interrupt has been generated.
HDMI Lvl INT Status 4 register consists of fields: HDMI_ENCRPT_A_ST and CABLE_DET_A_ST.
HDMI_ENCRPT_A_ST , IO, Address 0x70[2] (Read Only)
Latched status for Port A encryption detection interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
HDMI_ENCRPT_A_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
HDMI_ENCRPT_A_ST Description
0 (default) HDMI_ENCRPT_A_RAW has not changed. An interrupt has not been generated.
1 HDMI_ENCRPT_A_RAW has changed. An interrupt has been generated.
CABLE_DET_A_ST , IO, Address 0x70[0] (Read Only)
Latched status for Port A +5 V cable detection interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
CABLE_DET_A_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
CABLE_DET_A_ST Description
0 (default) CABLE_DET_A_RAW has not changed. Interrupt has not been generated from this register.
1 CABLE_DET_A_RAW has changed. Interrupt has been generated from this register.
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