Analog Devices Advantiv ADV7611 Hardware User's Manual page 57

Hardware User Guide
CHANNEL A
LSB MSB
FRAME N
LRCLK
SCLK
32 SCLKs
SLOT 1
AP
LEFT 1
MCLKOUT SETTING
The frequency of audio master clock MCLKOUT is set using the MCLK_FS_N[2:0] register, as shown in Equation 3, relationship between
MCLKOUT, MCLKFS_N, and f
MCLKOUT = (MCLKFS_N[2:0] + 1) × 128 × f
MCLK_FS_N[2:0] , Addr 4C (DPLL), Address 0xB5[2:0]
Selects the frequency of MCLK out as multiple of 128 fs.
Function
MCLK_FS_N[2:0]
000
001 (default)
010
011
100
101
110
111
Note that when I2S_TDM_MODE_ENABLE
V U C B
32 CLOCK SLOTS
Figure 19. AES3 Stream Timing Diagram
SLOT 2 SLOT 3
RIGHT 1 LEFT 2
MSB MSB – 1
.
s
S
Description
128 fs
256 fs
384 fs
512 fs
640 fs
768 fs
Not valid
Not valid
is set to 1, only the following fs ratios for MCLKOUT are valid: 1, 2, or 4.
CHANNEL B
LSB MSB V
32 CLOCK SLOTS
256 SCLKs
SLOT 4 SLOT 5
RIGHT 2 LEFT 3
LRCLK
SCLK
MSB – 2
AP
2
Figure 20. I S TDM Stream
(3)
Rev. A | Page 57 of 184
U C B
SLOT 6 SLOT 7
RIGHT 3 LEFT 4
UG-180
FRAME N + 1
SLOT 8
RIGHT 4